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d73f219dc31b9a1352a48db74c46bbecd2abf222
STM-Volume-Controller/Debug/Volume-Controller-STM.list
Lyubomir Penev d73f219dc3 Initialized project
2025-11-12 21:53:30 +01:00

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Volume-Controller-STM.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001f8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00003dd0 080001f8 080001f8 000011f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08003fc8 08003fc8 00004fc8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08003fe0 08003fe0 0000514c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08003fe0 08003fe0 00004fe0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08003fe8 08003fe8 0000514c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08003fe8 08003fe8 00004fe8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08003fec 08003fec 00004fec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08003ff0 00005000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .RxDecripSection 000000a0 2000000c 08003ffc 0000500c 2**2
CONTENTS, ALLOC, LOAD, DATA
10 .TxDecripSection 000000a0 200000ac 0800409c 000050ac 2**2
CONTENTS, ALLOC, LOAD, DATA
11 .bss 00000678 2000014c 0800413c 0000514c 2**2
ALLOC
12 ._user_heap_stack 00000604 200007c4 0800413c 000057c4 2**0
ALLOC
13 .ARM.attributes 0000002e 00000000 00000000 0000514c 2**0
CONTENTS, READONLY
14 .debug_info 00011797 00000000 00000000 0000517a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 00002438 00000000 00000000 00016911 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_aranges 00000d20 00000000 00000000 00018d50 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_rnglists 00000a16 00000000 00000000 00019a70 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_macro 000284cd 00000000 00000000 0001a486 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_line 0000ffb6 00000000 00000000 00042953 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_str 000f8f59 00000000 00000000 00052909 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .comment 00000043 00000000 00000000 0014b862 2**0
CONTENTS, READONLY
22 .debug_frame 0000369c 00000000 00000000 0014b8a8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
23 .debug_line_str 0000006f 00000000 00000000 0014ef44 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001f8 <__do_global_dtors_aux>:
80001f8: b510 push {r4, lr}
80001fa: 4c05 ldr r4, [pc, #20] @ (8000210 <__do_global_dtors_aux+0x18>)
80001fc: 7823 ldrb r3, [r4, #0]
80001fe: b933 cbnz r3, 800020e <__do_global_dtors_aux+0x16>
8000200: 4b04 ldr r3, [pc, #16] @ (8000214 <__do_global_dtors_aux+0x1c>)
8000202: b113 cbz r3, 800020a <__do_global_dtors_aux+0x12>
8000204: 4804 ldr r0, [pc, #16] @ (8000218 <__do_global_dtors_aux+0x20>)
8000206: f3af 8000 nop.w
800020a: 2301 movs r3, #1
800020c: 7023 strb r3, [r4, #0]
800020e: bd10 pop {r4, pc}
8000210: 2000014c .word 0x2000014c
8000214: 00000000 .word 0x00000000
8000218: 08003fb0 .word 0x08003fb0
0800021c <frame_dummy>:
800021c: b508 push {r3, lr}
800021e: 4b03 ldr r3, [pc, #12] @ (800022c <frame_dummy+0x10>)
8000220: b11b cbz r3, 800022a <frame_dummy+0xe>
8000222: 4903 ldr r1, [pc, #12] @ (8000230 <frame_dummy+0x14>)
8000224: 4803 ldr r0, [pc, #12] @ (8000234 <frame_dummy+0x18>)
8000226: f3af 8000 nop.w
800022a: bd08 pop {r3, pc}
800022c: 00000000 .word 0x00000000
8000230: 20000150 .word 0x20000150
8000234: 08003fb0 .word 0x08003fb0
08000238 <__aeabi_uldivmod>:
8000238: b953 cbnz r3, 8000250 <__aeabi_uldivmod+0x18>
800023a: b94a cbnz r2, 8000250 <__aeabi_uldivmod+0x18>
800023c: 2900 cmp r1, #0
800023e: bf08 it eq
8000240: 2800 cmpeq r0, #0
8000242: bf1c itt ne
8000244: f04f 31ff movne.w r1, #4294967295
8000248: f04f 30ff movne.w r0, #4294967295
800024c: f000 b988 b.w 8000560 <__aeabi_idiv0>
8000250: f1ad 0c08 sub.w ip, sp, #8
8000254: e96d ce04 strd ip, lr, [sp, #-16]!
8000258: f000 f806 bl 8000268 <__udivmoddi4>
800025c: f8dd e004 ldr.w lr, [sp, #4]
8000260: e9dd 2302 ldrd r2, r3, [sp, #8]
8000264: b004 add sp, #16
8000266: 4770 bx lr
08000268 <__udivmoddi4>:
8000268: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800026c: 9d08 ldr r5, [sp, #32]
800026e: 468e mov lr, r1
8000270: 4604 mov r4, r0
8000272: 4688 mov r8, r1
8000274: 2b00 cmp r3, #0
8000276: d14a bne.n 800030e <__udivmoddi4+0xa6>
8000278: 428a cmp r2, r1
800027a: 4617 mov r7, r2
800027c: d962 bls.n 8000344 <__udivmoddi4+0xdc>
800027e: fab2 f682 clz r6, r2
8000282: b14e cbz r6, 8000298 <__udivmoddi4+0x30>
8000284: f1c6 0320 rsb r3, r6, #32
8000288: fa01 f806 lsl.w r8, r1, r6
800028c: fa20 f303 lsr.w r3, r0, r3
8000290: 40b7 lsls r7, r6
8000292: ea43 0808 orr.w r8, r3, r8
8000296: 40b4 lsls r4, r6
8000298: ea4f 4e17 mov.w lr, r7, lsr #16
800029c: fa1f fc87 uxth.w ip, r7
80002a0: fbb8 f1fe udiv r1, r8, lr
80002a4: 0c23 lsrs r3, r4, #16
80002a6: fb0e 8811 mls r8, lr, r1, r8
80002aa: ea43 4308 orr.w r3, r3, r8, lsl #16
80002ae: fb01 f20c mul.w r2, r1, ip
80002b2: 429a cmp r2, r3
80002b4: d909 bls.n 80002ca <__udivmoddi4+0x62>
80002b6: 18fb adds r3, r7, r3
80002b8: f101 30ff add.w r0, r1, #4294967295
80002bc: f080 80ea bcs.w 8000494 <__udivmoddi4+0x22c>
80002c0: 429a cmp r2, r3
80002c2: f240 80e7 bls.w 8000494 <__udivmoddi4+0x22c>
80002c6: 3902 subs r1, #2
80002c8: 443b add r3, r7
80002ca: 1a9a subs r2, r3, r2
80002cc: b2a3 uxth r3, r4
80002ce: fbb2 f0fe udiv r0, r2, lr
80002d2: fb0e 2210 mls r2, lr, r0, r2
80002d6: ea43 4302 orr.w r3, r3, r2, lsl #16
80002da: fb00 fc0c mul.w ip, r0, ip
80002de: 459c cmp ip, r3
80002e0: d909 bls.n 80002f6 <__udivmoddi4+0x8e>
80002e2: 18fb adds r3, r7, r3
80002e4: f100 32ff add.w r2, r0, #4294967295
80002e8: f080 80d6 bcs.w 8000498 <__udivmoddi4+0x230>
80002ec: 459c cmp ip, r3
80002ee: f240 80d3 bls.w 8000498 <__udivmoddi4+0x230>
80002f2: 443b add r3, r7
80002f4: 3802 subs r0, #2
80002f6: ea40 4001 orr.w r0, r0, r1, lsl #16
80002fa: eba3 030c sub.w r3, r3, ip
80002fe: 2100 movs r1, #0
8000300: b11d cbz r5, 800030a <__udivmoddi4+0xa2>
8000302: 40f3 lsrs r3, r6
8000304: 2200 movs r2, #0
8000306: e9c5 3200 strd r3, r2, [r5]
800030a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800030e: 428b cmp r3, r1
8000310: d905 bls.n 800031e <__udivmoddi4+0xb6>
8000312: b10d cbz r5, 8000318 <__udivmoddi4+0xb0>
8000314: e9c5 0100 strd r0, r1, [r5]
8000318: 2100 movs r1, #0
800031a: 4608 mov r0, r1
800031c: e7f5 b.n 800030a <__udivmoddi4+0xa2>
800031e: fab3 f183 clz r1, r3
8000322: 2900 cmp r1, #0
8000324: d146 bne.n 80003b4 <__udivmoddi4+0x14c>
8000326: 4573 cmp r3, lr
8000328: d302 bcc.n 8000330 <__udivmoddi4+0xc8>
800032a: 4282 cmp r2, r0
800032c: f200 8105 bhi.w 800053a <__udivmoddi4+0x2d2>
8000330: 1a84 subs r4, r0, r2
8000332: eb6e 0203 sbc.w r2, lr, r3
8000336: 2001 movs r0, #1
8000338: 4690 mov r8, r2
800033a: 2d00 cmp r5, #0
800033c: d0e5 beq.n 800030a <__udivmoddi4+0xa2>
800033e: e9c5 4800 strd r4, r8, [r5]
8000342: e7e2 b.n 800030a <__udivmoddi4+0xa2>
8000344: 2a00 cmp r2, #0
8000346: f000 8090 beq.w 800046a <__udivmoddi4+0x202>
800034a: fab2 f682 clz r6, r2
800034e: 2e00 cmp r6, #0
8000350: f040 80a4 bne.w 800049c <__udivmoddi4+0x234>
8000354: 1a8a subs r2, r1, r2
8000356: 0c03 lsrs r3, r0, #16
8000358: ea4f 4e17 mov.w lr, r7, lsr #16
800035c: b280 uxth r0, r0
800035e: b2bc uxth r4, r7
8000360: 2101 movs r1, #1
8000362: fbb2 fcfe udiv ip, r2, lr
8000366: fb0e 221c mls r2, lr, ip, r2
800036a: ea43 4302 orr.w r3, r3, r2, lsl #16
800036e: fb04 f20c mul.w r2, r4, ip
8000372: 429a cmp r2, r3
8000374: d907 bls.n 8000386 <__udivmoddi4+0x11e>
8000376: 18fb adds r3, r7, r3
8000378: f10c 38ff add.w r8, ip, #4294967295
800037c: d202 bcs.n 8000384 <__udivmoddi4+0x11c>
800037e: 429a cmp r2, r3
8000380: f200 80e0 bhi.w 8000544 <__udivmoddi4+0x2dc>
8000384: 46c4 mov ip, r8
8000386: 1a9b subs r3, r3, r2
8000388: fbb3 f2fe udiv r2, r3, lr
800038c: fb0e 3312 mls r3, lr, r2, r3
8000390: ea40 4303 orr.w r3, r0, r3, lsl #16
8000394: fb02 f404 mul.w r4, r2, r4
8000398: 429c cmp r4, r3
800039a: d907 bls.n 80003ac <__udivmoddi4+0x144>
800039c: 18fb adds r3, r7, r3
800039e: f102 30ff add.w r0, r2, #4294967295
80003a2: d202 bcs.n 80003aa <__udivmoddi4+0x142>
80003a4: 429c cmp r4, r3
80003a6: f200 80ca bhi.w 800053e <__udivmoddi4+0x2d6>
80003aa: 4602 mov r2, r0
80003ac: 1b1b subs r3, r3, r4
80003ae: ea42 400c orr.w r0, r2, ip, lsl #16
80003b2: e7a5 b.n 8000300 <__udivmoddi4+0x98>
80003b4: f1c1 0620 rsb r6, r1, #32
80003b8: 408b lsls r3, r1
80003ba: fa22 f706 lsr.w r7, r2, r6
80003be: 431f orrs r7, r3
80003c0: fa0e f401 lsl.w r4, lr, r1
80003c4: fa20 f306 lsr.w r3, r0, r6
80003c8: fa2e fe06 lsr.w lr, lr, r6
80003cc: ea4f 4917 mov.w r9, r7, lsr #16
80003d0: 4323 orrs r3, r4
80003d2: fa00 f801 lsl.w r8, r0, r1
80003d6: fa1f fc87 uxth.w ip, r7
80003da: fbbe f0f9 udiv r0, lr, r9
80003de: 0c1c lsrs r4, r3, #16
80003e0: fb09 ee10 mls lr, r9, r0, lr
80003e4: ea44 440e orr.w r4, r4, lr, lsl #16
80003e8: fb00 fe0c mul.w lr, r0, ip
80003ec: 45a6 cmp lr, r4
80003ee: fa02 f201 lsl.w r2, r2, r1
80003f2: d909 bls.n 8000408 <__udivmoddi4+0x1a0>
80003f4: 193c adds r4, r7, r4
80003f6: f100 3aff add.w sl, r0, #4294967295
80003fa: f080 809c bcs.w 8000536 <__udivmoddi4+0x2ce>
80003fe: 45a6 cmp lr, r4
8000400: f240 8099 bls.w 8000536 <__udivmoddi4+0x2ce>
8000404: 3802 subs r0, #2
8000406: 443c add r4, r7
8000408: eba4 040e sub.w r4, r4, lr
800040c: fa1f fe83 uxth.w lr, r3
8000410: fbb4 f3f9 udiv r3, r4, r9
8000414: fb09 4413 mls r4, r9, r3, r4
8000418: ea4e 4404 orr.w r4, lr, r4, lsl #16
800041c: fb03 fc0c mul.w ip, r3, ip
8000420: 45a4 cmp ip, r4
8000422: d908 bls.n 8000436 <__udivmoddi4+0x1ce>
8000424: 193c adds r4, r7, r4
8000426: f103 3eff add.w lr, r3, #4294967295
800042a: f080 8082 bcs.w 8000532 <__udivmoddi4+0x2ca>
800042e: 45a4 cmp ip, r4
8000430: d97f bls.n 8000532 <__udivmoddi4+0x2ca>
8000432: 3b02 subs r3, #2
8000434: 443c add r4, r7
8000436: ea43 4000 orr.w r0, r3, r0, lsl #16
800043a: eba4 040c sub.w r4, r4, ip
800043e: fba0 ec02 umull lr, ip, r0, r2
8000442: 4564 cmp r4, ip
8000444: 4673 mov r3, lr
8000446: 46e1 mov r9, ip
8000448: d362 bcc.n 8000510 <__udivmoddi4+0x2a8>
800044a: d05f beq.n 800050c <__udivmoddi4+0x2a4>
800044c: b15d cbz r5, 8000466 <__udivmoddi4+0x1fe>
800044e: ebb8 0203 subs.w r2, r8, r3
8000452: eb64 0409 sbc.w r4, r4, r9
8000456: fa04 f606 lsl.w r6, r4, r6
800045a: fa22 f301 lsr.w r3, r2, r1
800045e: 431e orrs r6, r3
8000460: 40cc lsrs r4, r1
8000462: e9c5 6400 strd r6, r4, [r5]
8000466: 2100 movs r1, #0
8000468: e74f b.n 800030a <__udivmoddi4+0xa2>
800046a: fbb1 fcf2 udiv ip, r1, r2
800046e: 0c01 lsrs r1, r0, #16
8000470: ea41 410e orr.w r1, r1, lr, lsl #16
8000474: b280 uxth r0, r0
8000476: ea40 4201 orr.w r2, r0, r1, lsl #16
800047a: 463b mov r3, r7
800047c: 4638 mov r0, r7
800047e: 463c mov r4, r7
8000480: 46b8 mov r8, r7
8000482: 46be mov lr, r7
8000484: 2620 movs r6, #32
8000486: fbb1 f1f7 udiv r1, r1, r7
800048a: eba2 0208 sub.w r2, r2, r8
800048e: ea41 410c orr.w r1, r1, ip, lsl #16
8000492: e766 b.n 8000362 <__udivmoddi4+0xfa>
8000494: 4601 mov r1, r0
8000496: e718 b.n 80002ca <__udivmoddi4+0x62>
8000498: 4610 mov r0, r2
800049a: e72c b.n 80002f6 <__udivmoddi4+0x8e>
800049c: f1c6 0220 rsb r2, r6, #32
80004a0: fa2e f302 lsr.w r3, lr, r2
80004a4: 40b7 lsls r7, r6
80004a6: 40b1 lsls r1, r6
80004a8: fa20 f202 lsr.w r2, r0, r2
80004ac: ea4f 4e17 mov.w lr, r7, lsr #16
80004b0: 430a orrs r2, r1
80004b2: fbb3 f8fe udiv r8, r3, lr
80004b6: b2bc uxth r4, r7
80004b8: fb0e 3318 mls r3, lr, r8, r3
80004bc: 0c11 lsrs r1, r2, #16
80004be: ea41 4103 orr.w r1, r1, r3, lsl #16
80004c2: fb08 f904 mul.w r9, r8, r4
80004c6: 40b0 lsls r0, r6
80004c8: 4589 cmp r9, r1
80004ca: ea4f 4310 mov.w r3, r0, lsr #16
80004ce: b280 uxth r0, r0
80004d0: d93e bls.n 8000550 <__udivmoddi4+0x2e8>
80004d2: 1879 adds r1, r7, r1
80004d4: f108 3cff add.w ip, r8, #4294967295
80004d8: d201 bcs.n 80004de <__udivmoddi4+0x276>
80004da: 4589 cmp r9, r1
80004dc: d81f bhi.n 800051e <__udivmoddi4+0x2b6>
80004de: eba1 0109 sub.w r1, r1, r9
80004e2: fbb1 f9fe udiv r9, r1, lr
80004e6: fb09 f804 mul.w r8, r9, r4
80004ea: fb0e 1119 mls r1, lr, r9, r1
80004ee: b292 uxth r2, r2
80004f0: ea42 4201 orr.w r2, r2, r1, lsl #16
80004f4: 4542 cmp r2, r8
80004f6: d229 bcs.n 800054c <__udivmoddi4+0x2e4>
80004f8: 18ba adds r2, r7, r2
80004fa: f109 31ff add.w r1, r9, #4294967295
80004fe: d2c4 bcs.n 800048a <__udivmoddi4+0x222>
8000500: 4542 cmp r2, r8
8000502: d2c2 bcs.n 800048a <__udivmoddi4+0x222>
8000504: f1a9 0102 sub.w r1, r9, #2
8000508: 443a add r2, r7
800050a: e7be b.n 800048a <__udivmoddi4+0x222>
800050c: 45f0 cmp r8, lr
800050e: d29d bcs.n 800044c <__udivmoddi4+0x1e4>
8000510: ebbe 0302 subs.w r3, lr, r2
8000514: eb6c 0c07 sbc.w ip, ip, r7
8000518: 3801 subs r0, #1
800051a: 46e1 mov r9, ip
800051c: e796 b.n 800044c <__udivmoddi4+0x1e4>
800051e: eba7 0909 sub.w r9, r7, r9
8000522: 4449 add r1, r9
8000524: f1a8 0c02 sub.w ip, r8, #2
8000528: fbb1 f9fe udiv r9, r1, lr
800052c: fb09 f804 mul.w r8, r9, r4
8000530: e7db b.n 80004ea <__udivmoddi4+0x282>
8000532: 4673 mov r3, lr
8000534: e77f b.n 8000436 <__udivmoddi4+0x1ce>
8000536: 4650 mov r0, sl
8000538: e766 b.n 8000408 <__udivmoddi4+0x1a0>
800053a: 4608 mov r0, r1
800053c: e6fd b.n 800033a <__udivmoddi4+0xd2>
800053e: 443b add r3, r7
8000540: 3a02 subs r2, #2
8000542: e733 b.n 80003ac <__udivmoddi4+0x144>
8000544: f1ac 0c02 sub.w ip, ip, #2
8000548: 443b add r3, r7
800054a: e71c b.n 8000386 <__udivmoddi4+0x11e>
800054c: 4649 mov r1, r9
800054e: e79c b.n 800048a <__udivmoddi4+0x222>
8000550: eba1 0109 sub.w r1, r1, r9
8000554: 46c4 mov ip, r8
8000556: fbb1 f9fe udiv r9, r1, lr
800055a: fb09 f804 mul.w r8, r9, r4
800055e: e7c4 b.n 80004ea <__udivmoddi4+0x282>
08000560 <__aeabi_idiv0>:
8000560: 4770 bx lr
8000562: bf00 nop
08000564 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000564: b580 push {r7, lr}
8000566: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000568: f000 fc07 bl 8000d7a <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800056c: f000 f81e bl 80005ac <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000570: f000 f93a bl 80007e8 <MX_GPIO_Init>
MX_ETH_Init();
8000574: f000 f88c bl 8000690 <MX_ETH_Init>
MX_USART3_UART_Init();
8000578: f000 f8d8 bl 800072c <MX_USART3_UART_Init>
MX_USB_OTG_FS_PCD_Init();
800057c: f000 f906 bl 800078c <MX_USB_OTG_FS_PCD_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
HAL_GPIO_TogglePin(LD1_GPIO_Port, LD1_Pin);
8000580: 2101 movs r1, #1
8000582: 4809 ldr r0, [pc, #36] @ (80005a8 <main+0x44>)
8000584: f001 fa73 bl 8001a6e <HAL_GPIO_TogglePin>
HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin);
8000588: 2180 movs r1, #128 @ 0x80
800058a: 4807 ldr r0, [pc, #28] @ (80005a8 <main+0x44>)
800058c: f001 fa6f bl 8001a6e <HAL_GPIO_TogglePin>
HAL_GPIO_TogglePin(LD3_GPIO_Port, LD3_Pin);
8000590: f44f 4180 mov.w r1, #16384 @ 0x4000
8000594: 4804 ldr r0, [pc, #16] @ (80005a8 <main+0x44>)
8000596: f001 fa6a bl 8001a6e <HAL_GPIO_TogglePin>
HAL_Delay(500);
800059a: f44f 70fa mov.w r0, #500 @ 0x1f4
800059e: f000 fc49 bl 8000e34 <HAL_Delay>
HAL_GPIO_TogglePin(LD1_GPIO_Port, LD1_Pin);
80005a2: bf00 nop
80005a4: e7ec b.n 8000580 <main+0x1c>
80005a6: bf00 nop
80005a8: 40020400 .word 0x40020400
080005ac <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80005ac: b580 push {r7, lr}
80005ae: b094 sub sp, #80 @ 0x50
80005b0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80005b2: f107 031c add.w r3, r7, #28
80005b6: 2234 movs r2, #52 @ 0x34
80005b8: 2100 movs r1, #0
80005ba: 4618 mov r0, r3
80005bc: f003 fccc bl 8003f58 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80005c0: f107 0308 add.w r3, r7, #8
80005c4: 2200 movs r2, #0
80005c6: 601a str r2, [r3, #0]
80005c8: 605a str r2, [r3, #4]
80005ca: 609a str r2, [r3, #8]
80005cc: 60da str r2, [r3, #12]
80005ce: 611a str r2, [r3, #16]
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
80005d0: f001 fba2 bl 8001d18 <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80005d4: 4b2c ldr r3, [pc, #176] @ (8000688 <SystemClock_Config+0xdc>)
80005d6: 6c1b ldr r3, [r3, #64] @ 0x40
80005d8: 4a2b ldr r2, [pc, #172] @ (8000688 <SystemClock_Config+0xdc>)
80005da: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80005de: 6413 str r3, [r2, #64] @ 0x40
80005e0: 4b29 ldr r3, [pc, #164] @ (8000688 <SystemClock_Config+0xdc>)
80005e2: 6c1b ldr r3, [r3, #64] @ 0x40
80005e4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80005e8: 607b str r3, [r7, #4]
80005ea: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
80005ec: 4b27 ldr r3, [pc, #156] @ (800068c <SystemClock_Config+0xe0>)
80005ee: 681b ldr r3, [r3, #0]
80005f0: f423 4340 bic.w r3, r3, #49152 @ 0xc000
80005f4: 4a25 ldr r2, [pc, #148] @ (800068c <SystemClock_Config+0xe0>)
80005f6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80005fa: 6013 str r3, [r2, #0]
80005fc: 4b23 ldr r3, [pc, #140] @ (800068c <SystemClock_Config+0xe0>)
80005fe: 681b ldr r3, [r3, #0]
8000600: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000604: 603b str r3, [r7, #0]
8000606: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000608: 2301 movs r3, #1
800060a: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
800060c: f44f 23a0 mov.w r3, #327680 @ 0x50000
8000610: 623b str r3, [r7, #32]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000612: 2302 movs r3, #2
8000614: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000616: f44f 0380 mov.w r3, #4194304 @ 0x400000
800061a: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = 4;
800061c: 2304 movs r3, #4
800061e: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 96;
8000620: 2360 movs r3, #96 @ 0x60
8000622: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000624: 2302 movs r3, #2
8000626: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = 4;
8000628: 2304 movs r3, #4
800062a: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = 2;
800062c: 2302 movs r3, #2
800062e: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000630: f107 031c add.w r3, r7, #28
8000634: 4618 mov r0, r3
8000636: f001 fbcf bl 8001dd8 <HAL_RCC_OscConfig>
800063a: 4603 mov r3, r0
800063c: 2b00 cmp r3, #0
800063e: d001 beq.n 8000644 <SystemClock_Config+0x98>
{
Error_Handler();
8000640: f000 f974 bl 800092c <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000644: f001 fb78 bl 8001d38 <HAL_PWREx_EnableOverDrive>
8000648: 4603 mov r3, r0
800064a: 2b00 cmp r3, #0
800064c: d001 beq.n 8000652 <SystemClock_Config+0xa6>
{
Error_Handler();
800064e: f000 f96d bl 800092c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000652: 230f movs r3, #15
8000654: 60bb str r3, [r7, #8]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000656: 2302 movs r3, #2
8000658: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800065a: 2300 movs r3, #0
800065c: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800065e: f44f 5380 mov.w r3, #4096 @ 0x1000
8000662: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000664: 2300 movs r3, #0
8000666: 61bb str r3, [r7, #24]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
8000668: f107 0308 add.w r3, r7, #8
800066c: 2103 movs r1, #3
800066e: 4618 mov r0, r3
8000670: f001 fe60 bl 8002334 <HAL_RCC_ClockConfig>
8000674: 4603 mov r3, r0
8000676: 2b00 cmp r3, #0
8000678: d001 beq.n 800067e <SystemClock_Config+0xd2>
{
Error_Handler();
800067a: f000 f957 bl 800092c <Error_Handler>
}
}
800067e: bf00 nop
8000680: 3750 adds r7, #80 @ 0x50
8000682: 46bd mov sp, r7
8000684: bd80 pop {r7, pc}
8000686: bf00 nop
8000688: 40023800 .word 0x40023800
800068c: 40007000 .word 0x40007000
08000690 <MX_ETH_Init>:
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static void MX_ETH_Init(void)
{
8000690: b580 push {r7, lr}
8000692: af00 add r7, sp, #0
static uint8_t MACAddr[6];
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth.Instance = ETH;
8000694: 4b1f ldr r3, [pc, #124] @ (8000714 <MX_ETH_Init+0x84>)
8000696: 4a20 ldr r2, [pc, #128] @ (8000718 <MX_ETH_Init+0x88>)
8000698: 601a str r2, [r3, #0]
MACAddr[0] = 0x00;
800069a: 4b20 ldr r3, [pc, #128] @ (800071c <MX_ETH_Init+0x8c>)
800069c: 2200 movs r2, #0
800069e: 701a strb r2, [r3, #0]
MACAddr[1] = 0x80;
80006a0: 4b1e ldr r3, [pc, #120] @ (800071c <MX_ETH_Init+0x8c>)
80006a2: 2280 movs r2, #128 @ 0x80
80006a4: 705a strb r2, [r3, #1]
MACAddr[2] = 0xE1;
80006a6: 4b1d ldr r3, [pc, #116] @ (800071c <MX_ETH_Init+0x8c>)
80006a8: 22e1 movs r2, #225 @ 0xe1
80006aa: 709a strb r2, [r3, #2]
MACAddr[3] = 0x00;
80006ac: 4b1b ldr r3, [pc, #108] @ (800071c <MX_ETH_Init+0x8c>)
80006ae: 2200 movs r2, #0
80006b0: 70da strb r2, [r3, #3]
MACAddr[4] = 0x00;
80006b2: 4b1a ldr r3, [pc, #104] @ (800071c <MX_ETH_Init+0x8c>)
80006b4: 2200 movs r2, #0
80006b6: 711a strb r2, [r3, #4]
MACAddr[5] = 0x00;
80006b8: 4b18 ldr r3, [pc, #96] @ (800071c <MX_ETH_Init+0x8c>)
80006ba: 2200 movs r2, #0
80006bc: 715a strb r2, [r3, #5]
heth.Init.MACAddr = &MACAddr[0];
80006be: 4b15 ldr r3, [pc, #84] @ (8000714 <MX_ETH_Init+0x84>)
80006c0: 4a16 ldr r2, [pc, #88] @ (800071c <MX_ETH_Init+0x8c>)
80006c2: 605a str r2, [r3, #4]
heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
80006c4: 4b13 ldr r3, [pc, #76] @ (8000714 <MX_ETH_Init+0x84>)
80006c6: f44f 0200 mov.w r2, #8388608 @ 0x800000
80006ca: 609a str r2, [r3, #8]
heth.Init.TxDesc = DMATxDscrTab;
80006cc: 4b11 ldr r3, [pc, #68] @ (8000714 <MX_ETH_Init+0x84>)
80006ce: 4a14 ldr r2, [pc, #80] @ (8000720 <MX_ETH_Init+0x90>)
80006d0: 60da str r2, [r3, #12]
heth.Init.RxDesc = DMARxDscrTab;
80006d2: 4b10 ldr r3, [pc, #64] @ (8000714 <MX_ETH_Init+0x84>)
80006d4: 4a13 ldr r2, [pc, #76] @ (8000724 <MX_ETH_Init+0x94>)
80006d6: 611a str r2, [r3, #16]
heth.Init.RxBuffLen = 1524;
80006d8: 4b0e ldr r3, [pc, #56] @ (8000714 <MX_ETH_Init+0x84>)
80006da: f240 52f4 movw r2, #1524 @ 0x5f4
80006de: 615a str r2, [r3, #20]
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if (HAL_ETH_Init(&heth) != HAL_OK)
80006e0: 480c ldr r0, [pc, #48] @ (8000714 <MX_ETH_Init+0x84>)
80006e2: f000 fcb1 bl 8001048 <HAL_ETH_Init>
80006e6: 4603 mov r3, r0
80006e8: 2b00 cmp r3, #0
80006ea: d001 beq.n 80006f0 <MX_ETH_Init+0x60>
{
Error_Handler();
80006ec: f000 f91e bl 800092c <Error_Handler>
}
memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
80006f0: 2238 movs r2, #56 @ 0x38
80006f2: 2100 movs r1, #0
80006f4: 480c ldr r0, [pc, #48] @ (8000728 <MX_ETH_Init+0x98>)
80006f6: f003 fc2f bl 8003f58 <memset>
TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
80006fa: 4b0b ldr r3, [pc, #44] @ (8000728 <MX_ETH_Init+0x98>)
80006fc: 2221 movs r2, #33 @ 0x21
80006fe: 601a str r2, [r3, #0]
TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
8000700: 4b09 ldr r3, [pc, #36] @ (8000728 <MX_ETH_Init+0x98>)
8000702: f44f 0240 mov.w r2, #12582912 @ 0xc00000
8000706: 615a str r2, [r3, #20]
TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
8000708: 4b07 ldr r3, [pc, #28] @ (8000728 <MX_ETH_Init+0x98>)
800070a: 2200 movs r2, #0
800070c: 611a str r2, [r3, #16]
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
800070e: bf00 nop
8000710: bd80 pop {r7, pc}
8000712: bf00 nop
8000714: 200001a0 .word 0x200001a0
8000718: 40028000 .word 0x40028000
800071c: 200007b8 .word 0x200007b8
8000720: 200000ac .word 0x200000ac
8000724: 2000000c .word 0x2000000c
8000728: 20000168 .word 0x20000168
0800072c <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
800072c: b580 push {r7, lr}
800072e: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8000730: 4b14 ldr r3, [pc, #80] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000732: 4a15 ldr r2, [pc, #84] @ (8000788 <MX_USART3_UART_Init+0x5c>)
8000734: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
8000736: 4b13 ldr r3, [pc, #76] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000738: f44f 32e1 mov.w r2, #115200 @ 0x1c200
800073c: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
800073e: 4b11 ldr r3, [pc, #68] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000740: 2200 movs r2, #0
8000742: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
8000744: 4b0f ldr r3, [pc, #60] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000746: 2200 movs r2, #0
8000748: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
800074a: 4b0e ldr r3, [pc, #56] @ (8000784 <MX_USART3_UART_Init+0x58>)
800074c: 2200 movs r2, #0
800074e: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
8000750: 4b0c ldr r3, [pc, #48] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000752: 220c movs r2, #12
8000754: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000756: 4b0b ldr r3, [pc, #44] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000758: 2200 movs r2, #0
800075a: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
800075c: 4b09 ldr r3, [pc, #36] @ (8000784 <MX_USART3_UART_Init+0x58>)
800075e: 2200 movs r2, #0
8000760: 61da str r2, [r3, #28]
huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000762: 4b08 ldr r3, [pc, #32] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000764: 2200 movs r2, #0
8000766: 621a str r2, [r3, #32]
huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000768: 4b06 ldr r3, [pc, #24] @ (8000784 <MX_USART3_UART_Init+0x58>)
800076a: 2200 movs r2, #0
800076c: 625a str r2, [r3, #36] @ 0x24
if (HAL_UART_Init(&huart3) != HAL_OK)
800076e: 4805 ldr r0, [pc, #20] @ (8000784 <MX_USART3_UART_Init+0x58>)
8000770: f002 fc2e bl 8002fd0 <HAL_UART_Init>
8000774: 4603 mov r3, r0
8000776: 2b00 cmp r3, #0
8000778: d001 beq.n 800077e <MX_USART3_UART_Init+0x52>
{
Error_Handler();
800077a: f000 f8d7 bl 800092c <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
800077e: bf00 nop
8000780: bd80 pop {r7, pc}
8000782: bf00 nop
8000784: 20000250 .word 0x20000250
8000788: 40004800 .word 0x40004800
0800078c <MX_USB_OTG_FS_PCD_Init>:
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_PCD_Init(void)
{
800078c: b580 push {r7, lr}
800078e: af00 add r7, sp, #0
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
8000790: 4b14 ldr r3, [pc, #80] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
8000792: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
8000796: 601a str r2, [r3, #0]
hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
8000798: 4b12 ldr r3, [pc, #72] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
800079a: 2206 movs r2, #6
800079c: 711a strb r2, [r3, #4]
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
800079e: 4b11 ldr r3, [pc, #68] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007a0: 2202 movs r2, #2
80007a2: 71da strb r2, [r3, #7]
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
80007a4: 4b0f ldr r3, [pc, #60] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007a6: 2200 movs r2, #0
80007a8: 719a strb r2, [r3, #6]
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
80007aa: 4b0e ldr r3, [pc, #56] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007ac: 2202 movs r2, #2
80007ae: 725a strb r2, [r3, #9]
hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
80007b0: 4b0c ldr r3, [pc, #48] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007b2: 2201 movs r2, #1
80007b4: 729a strb r2, [r3, #10]
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
80007b6: 4b0b ldr r3, [pc, #44] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007b8: 2200 movs r2, #0
80007ba: 72da strb r2, [r3, #11]
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
80007bc: 4b09 ldr r3, [pc, #36] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007be: 2200 movs r2, #0
80007c0: 731a strb r2, [r3, #12]
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE;
80007c2: 4b08 ldr r3, [pc, #32] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007c4: 2201 movs r2, #1
80007c6: 739a strb r2, [r3, #14]
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
80007c8: 4b06 ldr r3, [pc, #24] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007ca: 2200 movs r2, #0
80007cc: 73da strb r2, [r3, #15]
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
80007ce: 4805 ldr r0, [pc, #20] @ (80007e4 <MX_USB_OTG_FS_PCD_Init+0x58>)
80007d0: f001 f967 bl 8001aa2 <HAL_PCD_Init>
80007d4: 4603 mov r3, r0
80007d6: 2b00 cmp r3, #0
80007d8: d001 beq.n 80007de <MX_USB_OTG_FS_PCD_Init+0x52>
{
Error_Handler();
80007da: f000 f8a7 bl 800092c <Error_Handler>
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
80007de: bf00 nop
80007e0: bd80 pop {r7, pc}
80007e2: bf00 nop
80007e4: 200002d8 .word 0x200002d8
080007e8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80007e8: b580 push {r7, lr}
80007ea: b08c sub sp, #48 @ 0x30
80007ec: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80007ee: f107 031c add.w r3, r7, #28
80007f2: 2200 movs r2, #0
80007f4: 601a str r2, [r3, #0]
80007f6: 605a str r2, [r3, #4]
80007f8: 609a str r2, [r3, #8]
80007fa: 60da str r2, [r3, #12]
80007fc: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80007fe: 4b47 ldr r3, [pc, #284] @ (800091c <MX_GPIO_Init+0x134>)
8000800: 6b1b ldr r3, [r3, #48] @ 0x30
8000802: 4a46 ldr r2, [pc, #280] @ (800091c <MX_GPIO_Init+0x134>)
8000804: f043 0304 orr.w r3, r3, #4
8000808: 6313 str r3, [r2, #48] @ 0x30
800080a: 4b44 ldr r3, [pc, #272] @ (800091c <MX_GPIO_Init+0x134>)
800080c: 6b1b ldr r3, [r3, #48] @ 0x30
800080e: f003 0304 and.w r3, r3, #4
8000812: 61bb str r3, [r7, #24]
8000814: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000816: 4b41 ldr r3, [pc, #260] @ (800091c <MX_GPIO_Init+0x134>)
8000818: 6b1b ldr r3, [r3, #48] @ 0x30
800081a: 4a40 ldr r2, [pc, #256] @ (800091c <MX_GPIO_Init+0x134>)
800081c: f043 0380 orr.w r3, r3, #128 @ 0x80
8000820: 6313 str r3, [r2, #48] @ 0x30
8000822: 4b3e ldr r3, [pc, #248] @ (800091c <MX_GPIO_Init+0x134>)
8000824: 6b1b ldr r3, [r3, #48] @ 0x30
8000826: f003 0380 and.w r3, r3, #128 @ 0x80
800082a: 617b str r3, [r7, #20]
800082c: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
800082e: 4b3b ldr r3, [pc, #236] @ (800091c <MX_GPIO_Init+0x134>)
8000830: 6b1b ldr r3, [r3, #48] @ 0x30
8000832: 4a3a ldr r2, [pc, #232] @ (800091c <MX_GPIO_Init+0x134>)
8000834: f043 0301 orr.w r3, r3, #1
8000838: 6313 str r3, [r2, #48] @ 0x30
800083a: 4b38 ldr r3, [pc, #224] @ (800091c <MX_GPIO_Init+0x134>)
800083c: 6b1b ldr r3, [r3, #48] @ 0x30
800083e: f003 0301 and.w r3, r3, #1
8000842: 613b str r3, [r7, #16]
8000844: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000846: 4b35 ldr r3, [pc, #212] @ (800091c <MX_GPIO_Init+0x134>)
8000848: 6b1b ldr r3, [r3, #48] @ 0x30
800084a: 4a34 ldr r2, [pc, #208] @ (800091c <MX_GPIO_Init+0x134>)
800084c: f043 0302 orr.w r3, r3, #2
8000850: 6313 str r3, [r2, #48] @ 0x30
8000852: 4b32 ldr r3, [pc, #200] @ (800091c <MX_GPIO_Init+0x134>)
8000854: 6b1b ldr r3, [r3, #48] @ 0x30
8000856: f003 0302 and.w r3, r3, #2
800085a: 60fb str r3, [r7, #12]
800085c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
800085e: 4b2f ldr r3, [pc, #188] @ (800091c <MX_GPIO_Init+0x134>)
8000860: 6b1b ldr r3, [r3, #48] @ 0x30
8000862: 4a2e ldr r2, [pc, #184] @ (800091c <MX_GPIO_Init+0x134>)
8000864: f043 0308 orr.w r3, r3, #8
8000868: 6313 str r3, [r2, #48] @ 0x30
800086a: 4b2c ldr r3, [pc, #176] @ (800091c <MX_GPIO_Init+0x134>)
800086c: 6b1b ldr r3, [r3, #48] @ 0x30
800086e: f003 0308 and.w r3, r3, #8
8000872: 60bb str r3, [r7, #8]
8000874: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000876: 4b29 ldr r3, [pc, #164] @ (800091c <MX_GPIO_Init+0x134>)
8000878: 6b1b ldr r3, [r3, #48] @ 0x30
800087a: 4a28 ldr r2, [pc, #160] @ (800091c <MX_GPIO_Init+0x134>)
800087c: f043 0340 orr.w r3, r3, #64 @ 0x40
8000880: 6313 str r3, [r2, #48] @ 0x30
8000882: 4b26 ldr r3, [pc, #152] @ (800091c <MX_GPIO_Init+0x134>)
8000884: 6b1b ldr r3, [r3, #48] @ 0x30
8000886: f003 0340 and.w r3, r3, #64 @ 0x40
800088a: 607b str r3, [r7, #4]
800088c: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET);
800088e: 2200 movs r2, #0
8000890: f244 0181 movw r1, #16513 @ 0x4081
8000894: 4822 ldr r0, [pc, #136] @ (8000920 <MX_GPIO_Init+0x138>)
8000896: f001 f8d1 bl 8001a3c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET);
800089a: 2200 movs r2, #0
800089c: 2140 movs r1, #64 @ 0x40
800089e: 4821 ldr r0, [pc, #132] @ (8000924 <MX_GPIO_Init+0x13c>)
80008a0: f001 f8cc bl 8001a3c <HAL_GPIO_WritePin>
/*Configure GPIO pin : USER_Btn_Pin */
GPIO_InitStruct.Pin = USER_Btn_Pin;
80008a4: f44f 5300 mov.w r3, #8192 @ 0x2000
80008a8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80008aa: f44f 1388 mov.w r3, #1114112 @ 0x110000
80008ae: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008b0: 2300 movs r3, #0
80008b2: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct);
80008b4: f107 031c add.w r3, r7, #28
80008b8: 4619 mov r1, r3
80008ba: 481b ldr r0, [pc, #108] @ (8000928 <MX_GPIO_Init+0x140>)
80008bc: f000 ff12 bl 80016e4 <HAL_GPIO_Init>
/*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */
GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin;
80008c0: f244 0381 movw r3, #16513 @ 0x4081
80008c4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008c6: 2301 movs r3, #1
80008c8: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008ca: 2300 movs r3, #0
80008cc: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008ce: 2300 movs r3, #0
80008d0: 62bb str r3, [r7, #40] @ 0x28
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80008d2: f107 031c add.w r3, r7, #28
80008d6: 4619 mov r1, r3
80008d8: 4811 ldr r0, [pc, #68] @ (8000920 <MX_GPIO_Init+0x138>)
80008da: f000 ff03 bl 80016e4 <HAL_GPIO_Init>
/*Configure GPIO pin : USB_PowerSwitchOn_Pin */
GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
80008de: 2340 movs r3, #64 @ 0x40
80008e0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008e2: 2301 movs r3, #1
80008e4: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008e6: 2300 movs r3, #0
80008e8: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008ea: 2300 movs r3, #0
80008ec: 62bb str r3, [r7, #40] @ 0x28
HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct);
80008ee: f107 031c add.w r3, r7, #28
80008f2: 4619 mov r1, r3
80008f4: 480b ldr r0, [pc, #44] @ (8000924 <MX_GPIO_Init+0x13c>)
80008f6: f000 fef5 bl 80016e4 <HAL_GPIO_Init>
/*Configure GPIO pin : USB_OverCurrent_Pin */
GPIO_InitStruct.Pin = USB_OverCurrent_Pin;
80008fa: 2380 movs r3, #128 @ 0x80
80008fc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80008fe: 2300 movs r3, #0
8000900: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000902: 2300 movs r3, #0
8000904: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8000906: f107 031c add.w r3, r7, #28
800090a: 4619 mov r1, r3
800090c: 4805 ldr r0, [pc, #20] @ (8000924 <MX_GPIO_Init+0x13c>)
800090e: f000 fee9 bl 80016e4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000912: bf00 nop
8000914: 3730 adds r7, #48 @ 0x30
8000916: 46bd mov sp, r7
8000918: bd80 pop {r7, pc}
800091a: bf00 nop
800091c: 40023800 .word 0x40023800
8000920: 40020400 .word 0x40020400
8000924: 40021800 .word 0x40021800
8000928: 40020800 .word 0x40020800
0800092c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800092c: b480 push {r7}
800092e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000930: b672 cpsid i
}
8000932: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000934: bf00 nop
8000936: e7fd b.n 8000934 <Error_Handler+0x8>
08000938 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000938: b480 push {r7}
800093a: b083 sub sp, #12
800093c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
800093e: 4b0f ldr r3, [pc, #60] @ (800097c <HAL_MspInit+0x44>)
8000940: 6c1b ldr r3, [r3, #64] @ 0x40
8000942: 4a0e ldr r2, [pc, #56] @ (800097c <HAL_MspInit+0x44>)
8000944: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000948: 6413 str r3, [r2, #64] @ 0x40
800094a: 4b0c ldr r3, [pc, #48] @ (800097c <HAL_MspInit+0x44>)
800094c: 6c1b ldr r3, [r3, #64] @ 0x40
800094e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000952: 607b str r3, [r7, #4]
8000954: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000956: 4b09 ldr r3, [pc, #36] @ (800097c <HAL_MspInit+0x44>)
8000958: 6c5b ldr r3, [r3, #68] @ 0x44
800095a: 4a08 ldr r2, [pc, #32] @ (800097c <HAL_MspInit+0x44>)
800095c: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000960: 6453 str r3, [r2, #68] @ 0x44
8000962: 4b06 ldr r3, [pc, #24] @ (800097c <HAL_MspInit+0x44>)
8000964: 6c5b ldr r3, [r3, #68] @ 0x44
8000966: f403 4380 and.w r3, r3, #16384 @ 0x4000
800096a: 603b str r3, [r7, #0]
800096c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800096e: bf00 nop
8000970: 370c adds r7, #12
8000972: 46bd mov sp, r7
8000974: f85d 7b04 ldr.w r7, [sp], #4
8000978: 4770 bx lr
800097a: bf00 nop
800097c: 40023800 .word 0x40023800
08000980 <HAL_ETH_MspInit>:
* This function configures the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
8000980: b580 push {r7, lr}
8000982: b08e sub sp, #56 @ 0x38
8000984: af00 add r7, sp, #0
8000986: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000988: f107 0324 add.w r3, r7, #36 @ 0x24
800098c: 2200 movs r2, #0
800098e: 601a str r2, [r3, #0]
8000990: 605a str r2, [r3, #4]
8000992: 609a str r2, [r3, #8]
8000994: 60da str r2, [r3, #12]
8000996: 611a str r2, [r3, #16]
if(heth->Instance==ETH)
8000998: 687b ldr r3, [r7, #4]
800099a: 681b ldr r3, [r3, #0]
800099c: 4a4e ldr r2, [pc, #312] @ (8000ad8 <HAL_ETH_MspInit+0x158>)
800099e: 4293 cmp r3, r2
80009a0: f040 8096 bne.w 8000ad0 <HAL_ETH_MspInit+0x150>
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH_CLK_ENABLE();
80009a4: 4b4d ldr r3, [pc, #308] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009a6: 6b1b ldr r3, [r3, #48] @ 0x30
80009a8: 4a4c ldr r2, [pc, #304] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009aa: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
80009ae: 6313 str r3, [r2, #48] @ 0x30
80009b0: 4b4a ldr r3, [pc, #296] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009b2: 6b1b ldr r3, [r3, #48] @ 0x30
80009b4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80009b8: 623b str r3, [r7, #32]
80009ba: 6a3b ldr r3, [r7, #32]
80009bc: 4b47 ldr r3, [pc, #284] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009be: 6b1b ldr r3, [r3, #48] @ 0x30
80009c0: 4a46 ldr r2, [pc, #280] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009c2: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
80009c6: 6313 str r3, [r2, #48] @ 0x30
80009c8: 4b44 ldr r3, [pc, #272] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009ca: 6b1b ldr r3, [r3, #48] @ 0x30
80009cc: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80009d0: 61fb str r3, [r7, #28]
80009d2: 69fb ldr r3, [r7, #28]
80009d4: 4b41 ldr r3, [pc, #260] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009d6: 6b1b ldr r3, [r3, #48] @ 0x30
80009d8: 4a40 ldr r2, [pc, #256] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009da: f043 6300 orr.w r3, r3, #134217728 @ 0x8000000
80009de: 6313 str r3, [r2, #48] @ 0x30
80009e0: 4b3e ldr r3, [pc, #248] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009e2: 6b1b ldr r3, [r3, #48] @ 0x30
80009e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
80009e8: 61bb str r3, [r7, #24]
80009ea: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOC_CLK_ENABLE();
80009ec: 4b3b ldr r3, [pc, #236] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009ee: 6b1b ldr r3, [r3, #48] @ 0x30
80009f0: 4a3a ldr r2, [pc, #232] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009f2: f043 0304 orr.w r3, r3, #4
80009f6: 6313 str r3, [r2, #48] @ 0x30
80009f8: 4b38 ldr r3, [pc, #224] @ (8000adc <HAL_ETH_MspInit+0x15c>)
80009fa: 6b1b ldr r3, [r3, #48] @ 0x30
80009fc: f003 0304 and.w r3, r3, #4
8000a00: 617b str r3, [r7, #20]
8000a02: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a04: 4b35 ldr r3, [pc, #212] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a06: 6b1b ldr r3, [r3, #48] @ 0x30
8000a08: 4a34 ldr r2, [pc, #208] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a0a: f043 0301 orr.w r3, r3, #1
8000a0e: 6313 str r3, [r2, #48] @ 0x30
8000a10: 4b32 ldr r3, [pc, #200] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a12: 6b1b ldr r3, [r3, #48] @ 0x30
8000a14: f003 0301 and.w r3, r3, #1
8000a18: 613b str r3, [r7, #16]
8000a1a: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000a1c: 4b2f ldr r3, [pc, #188] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a1e: 6b1b ldr r3, [r3, #48] @ 0x30
8000a20: 4a2e ldr r2, [pc, #184] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a22: f043 0302 orr.w r3, r3, #2
8000a26: 6313 str r3, [r2, #48] @ 0x30
8000a28: 4b2c ldr r3, [pc, #176] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a2a: 6b1b ldr r3, [r3, #48] @ 0x30
8000a2c: f003 0302 and.w r3, r3, #2
8000a30: 60fb str r3, [r7, #12]
8000a32: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000a34: 4b29 ldr r3, [pc, #164] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a36: 6b1b ldr r3, [r3, #48] @ 0x30
8000a38: 4a28 ldr r2, [pc, #160] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a3a: f043 0340 orr.w r3, r3, #64 @ 0x40
8000a3e: 6313 str r3, [r2, #48] @ 0x30
8000a40: 4b26 ldr r3, [pc, #152] @ (8000adc <HAL_ETH_MspInit+0x15c>)
8000a42: 6b1b ldr r3, [r3, #48] @ 0x30
8000a44: f003 0340 and.w r3, r3, #64 @ 0x40
8000a48: 60bb str r3, [r7, #8]
8000a4a: 68bb ldr r3, [r7, #8]
PC5 ------> ETH_RXD1
PB13 ------> ETH_TXD1
PG11 ------> ETH_TX_EN
PG13 ------> ETH_TXD0
*/
GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
8000a4c: 2332 movs r3, #50 @ 0x32
8000a4e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a50: 2302 movs r3, #2
8000a52: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a54: 2300 movs r3, #0
8000a56: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a58: 2303 movs r3, #3
8000a5a: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000a5c: 230b movs r3, #11
8000a5e: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000a60: f107 0324 add.w r3, r7, #36 @ 0x24
8000a64: 4619 mov r1, r3
8000a66: 481e ldr r0, [pc, #120] @ (8000ae0 <HAL_ETH_MspInit+0x160>)
8000a68: f000 fe3c bl 80016e4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
8000a6c: 2386 movs r3, #134 @ 0x86
8000a6e: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a70: 2302 movs r3, #2
8000a72: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a74: 2300 movs r3, #0
8000a76: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a78: 2303 movs r3, #3
8000a7a: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000a7c: 230b movs r3, #11
8000a7e: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a80: f107 0324 add.w r3, r7, #36 @ 0x24
8000a84: 4619 mov r1, r3
8000a86: 4817 ldr r0, [pc, #92] @ (8000ae4 <HAL_ETH_MspInit+0x164>)
8000a88: f000 fe2c bl 80016e4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_TXD1_Pin;
8000a8c: f44f 5300 mov.w r3, #8192 @ 0x2000
8000a90: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a92: 2302 movs r3, #2
8000a94: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a96: 2300 movs r3, #0
8000a98: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a9a: 2303 movs r3, #3
8000a9c: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000a9e: 230b movs r3, #11
8000aa0: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
8000aa2: f107 0324 add.w r3, r7, #36 @ 0x24
8000aa6: 4619 mov r1, r3
8000aa8: 480f ldr r0, [pc, #60] @ (8000ae8 <HAL_ETH_MspInit+0x168>)
8000aaa: f000 fe1b bl 80016e4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
8000aae: f44f 5320 mov.w r3, #10240 @ 0x2800
8000ab2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ab4: 2302 movs r3, #2
8000ab6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ab8: 2300 movs r3, #0
8000aba: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000abc: 2303 movs r3, #3
8000abe: 633b str r3, [r7, #48] @ 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
8000ac0: 230b movs r3, #11
8000ac2: 637b str r3, [r7, #52] @ 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000ac4: f107 0324 add.w r3, r7, #36 @ 0x24
8000ac8: 4619 mov r1, r3
8000aca: 4808 ldr r0, [pc, #32] @ (8000aec <HAL_ETH_MspInit+0x16c>)
8000acc: f000 fe0a bl 80016e4 <HAL_GPIO_Init>
/* USER CODE END ETH_MspInit 1 */
}
}
8000ad0: bf00 nop
8000ad2: 3738 adds r7, #56 @ 0x38
8000ad4: 46bd mov sp, r7
8000ad6: bd80 pop {r7, pc}
8000ad8: 40028000 .word 0x40028000
8000adc: 40023800 .word 0x40023800
8000ae0: 40020800 .word 0x40020800
8000ae4: 40020000 .word 0x40020000
8000ae8: 40020400 .word 0x40020400
8000aec: 40021800 .word 0x40021800
08000af0 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000af0: b580 push {r7, lr}
8000af2: b0ae sub sp, #184 @ 0xb8
8000af4: af00 add r7, sp, #0
8000af6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000af8: f107 03a4 add.w r3, r7, #164 @ 0xa4
8000afc: 2200 movs r2, #0
8000afe: 601a str r2, [r3, #0]
8000b00: 605a str r2, [r3, #4]
8000b02: 609a str r2, [r3, #8]
8000b04: 60da str r2, [r3, #12]
8000b06: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000b08: f107 0314 add.w r3, r7, #20
8000b0c: 2290 movs r2, #144 @ 0x90
8000b0e: 2100 movs r1, #0
8000b10: 4618 mov r0, r3
8000b12: f003 fa21 bl 8003f58 <memset>
if(huart->Instance==USART3)
8000b16: 687b ldr r3, [r7, #4]
8000b18: 681b ldr r3, [r3, #0]
8000b1a: 4a22 ldr r2, [pc, #136] @ (8000ba4 <HAL_UART_MspInit+0xb4>)
8000b1c: 4293 cmp r3, r2
8000b1e: d13c bne.n 8000b9a <HAL_UART_MspInit+0xaa>
/* USER CODE END USART3_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3;
8000b20: f44f 7380 mov.w r3, #256 @ 0x100
8000b24: 617b str r3, [r7, #20]
PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
8000b26: 2300 movs r3, #0
8000b28: 663b str r3, [r7, #96] @ 0x60
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000b2a: f107 0314 add.w r3, r7, #20
8000b2e: 4618 mov r0, r3
8000b30: f001 fe26 bl 8002780 <HAL_RCCEx_PeriphCLKConfig>
8000b34: 4603 mov r3, r0
8000b36: 2b00 cmp r3, #0
8000b38: d001 beq.n 8000b3e <HAL_UART_MspInit+0x4e>
{
Error_Handler();
8000b3a: f7ff fef7 bl 800092c <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART3_CLK_ENABLE();
8000b3e: 4b1a ldr r3, [pc, #104] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b40: 6c1b ldr r3, [r3, #64] @ 0x40
8000b42: 4a19 ldr r2, [pc, #100] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b44: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8000b48: 6413 str r3, [r2, #64] @ 0x40
8000b4a: 4b17 ldr r3, [pc, #92] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b4c: 6c1b ldr r3, [r3, #64] @ 0x40
8000b4e: f403 2380 and.w r3, r3, #262144 @ 0x40000
8000b52: 613b str r3, [r7, #16]
8000b54: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000b56: 4b14 ldr r3, [pc, #80] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b58: 6b1b ldr r3, [r3, #48] @ 0x30
8000b5a: 4a13 ldr r2, [pc, #76] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b5c: f043 0308 orr.w r3, r3, #8
8000b60: 6313 str r3, [r2, #48] @ 0x30
8000b62: 4b11 ldr r3, [pc, #68] @ (8000ba8 <HAL_UART_MspInit+0xb8>)
8000b64: 6b1b ldr r3, [r3, #48] @ 0x30
8000b66: f003 0308 and.w r3, r3, #8
8000b6a: 60fb str r3, [r7, #12]
8000b6c: 68fb ldr r3, [r7, #12]
/**USART3 GPIO Configuration
PD8 ------> USART3_TX
PD9 ------> USART3_RX
*/
GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
8000b6e: f44f 7340 mov.w r3, #768 @ 0x300
8000b72: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b76: 2302 movs r3, #2
8000b78: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b7c: 2300 movs r3, #0
8000b7e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b82: 2303 movs r3, #3
8000b84: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8000b88: 2307 movs r3, #7
8000b8a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000b8e: f107 03a4 add.w r3, r7, #164 @ 0xa4
8000b92: 4619 mov r1, r3
8000b94: 4805 ldr r0, [pc, #20] @ (8000bac <HAL_UART_MspInit+0xbc>)
8000b96: f000 fda5 bl 80016e4 <HAL_GPIO_Init>
/* USER CODE END USART3_MspInit 1 */
}
}
8000b9a: bf00 nop
8000b9c: 37b8 adds r7, #184 @ 0xb8
8000b9e: 46bd mov sp, r7
8000ba0: bd80 pop {r7, pc}
8000ba2: bf00 nop
8000ba4: 40004800 .word 0x40004800
8000ba8: 40023800 .word 0x40023800
8000bac: 40020c00 .word 0x40020c00
08000bb0 <HAL_PCD_MspInit>:
* This function configures the hardware resources used in this example
* @param hpcd: PCD handle pointer
* @retval None
*/
void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
{
8000bb0: b580 push {r7, lr}
8000bb2: b0ae sub sp, #184 @ 0xb8
8000bb4: af00 add r7, sp, #0
8000bb6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000bb8: f107 03a4 add.w r3, r7, #164 @ 0xa4
8000bbc: 2200 movs r2, #0
8000bbe: 601a str r2, [r3, #0]
8000bc0: 605a str r2, [r3, #4]
8000bc2: 609a str r2, [r3, #8]
8000bc4: 60da str r2, [r3, #12]
8000bc6: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000bc8: f107 0314 add.w r3, r7, #20
8000bcc: 2290 movs r2, #144 @ 0x90
8000bce: 2100 movs r1, #0
8000bd0: 4618 mov r0, r3
8000bd2: f003 f9c1 bl 8003f58 <memset>
if(hpcd->Instance==USB_OTG_FS)
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 681b ldr r3, [r3, #0]
8000bda: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8000bde: d159 bne.n 8000c94 <HAL_PCD_MspInit+0xe4>
/* USER CODE END USB_OTG_FS_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
8000be0: f44f 1300 mov.w r3, #2097152 @ 0x200000
8000be4: 617b str r3, [r7, #20]
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
8000be6: 2300 movs r3, #0
8000be8: f8c7 3090 str.w r3, [r7, #144] @ 0x90
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000bec: f107 0314 add.w r3, r7, #20
8000bf0: 4618 mov r0, r3
8000bf2: f001 fdc5 bl 8002780 <HAL_RCCEx_PeriphCLKConfig>
8000bf6: 4603 mov r3, r0
8000bf8: 2b00 cmp r3, #0
8000bfa: d001 beq.n 8000c00 <HAL_PCD_MspInit+0x50>
{
Error_Handler();
8000bfc: f7ff fe96 bl 800092c <Error_Handler>
}
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c00: 4b26 ldr r3, [pc, #152] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c02: 6b1b ldr r3, [r3, #48] @ 0x30
8000c04: 4a25 ldr r2, [pc, #148] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c06: f043 0301 orr.w r3, r3, #1
8000c0a: 6313 str r3, [r2, #48] @ 0x30
8000c0c: 4b23 ldr r3, [pc, #140] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c0e: 6b1b ldr r3, [r3, #48] @ 0x30
8000c10: f003 0301 and.w r3, r3, #1
8000c14: 613b str r3, [r7, #16]
8000c16: 693b ldr r3, [r7, #16]
PA9 ------> USB_OTG_FS_VBUS
PA10 ------> USB_OTG_FS_ID
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin;
8000c18: f44f 53e8 mov.w r3, #7424 @ 0x1d00
8000c1c: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c20: 2302 movs r3, #2
8000c22: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c26: 2300 movs r3, #0
8000c28: f8c7 30ac str.w r3, [r7, #172] @ 0xac
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c2c: 2303 movs r3, #3
8000c2e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8000c32: 230a movs r3, #10
8000c34: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c38: f107 03a4 add.w r3, r7, #164 @ 0xa4
8000c3c: 4619 mov r1, r3
8000c3e: 4818 ldr r0, [pc, #96] @ (8000ca0 <HAL_PCD_MspInit+0xf0>)
8000c40: f000 fd50 bl 80016e4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = USB_VBUS_Pin;
8000c44: f44f 7300 mov.w r3, #512 @ 0x200
8000c48: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000c4c: 2300 movs r3, #0
8000c4e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c52: 2300 movs r3, #0
8000c54: f8c7 30ac str.w r3, [r7, #172] @ 0xac
HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct);
8000c58: f107 03a4 add.w r3, r7, #164 @ 0xa4
8000c5c: 4619 mov r1, r3
8000c5e: 4810 ldr r0, [pc, #64] @ (8000ca0 <HAL_PCD_MspInit+0xf0>)
8000c60: f000 fd40 bl 80016e4 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
8000c64: 4b0d ldr r3, [pc, #52] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c66: 6b5b ldr r3, [r3, #52] @ 0x34
8000c68: 4a0c ldr r2, [pc, #48] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c6a: f043 0380 orr.w r3, r3, #128 @ 0x80
8000c6e: 6353 str r3, [r2, #52] @ 0x34
8000c70: 4b0a ldr r3, [pc, #40] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c72: 6b5b ldr r3, [r3, #52] @ 0x34
8000c74: f003 0380 and.w r3, r3, #128 @ 0x80
8000c78: 60fb str r3, [r7, #12]
8000c7a: 68fb ldr r3, [r7, #12]
8000c7c: 4b07 ldr r3, [pc, #28] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c7e: 6c5b ldr r3, [r3, #68] @ 0x44
8000c80: 4a06 ldr r2, [pc, #24] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c82: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000c86: 6453 str r3, [r2, #68] @ 0x44
8000c88: 4b04 ldr r3, [pc, #16] @ (8000c9c <HAL_PCD_MspInit+0xec>)
8000c8a: 6c5b ldr r3, [r3, #68] @ 0x44
8000c8c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8000c90: 60bb str r3, [r7, #8]
8000c92: 68bb ldr r3, [r7, #8]
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
8000c94: bf00 nop
8000c96: 37b8 adds r7, #184 @ 0xb8
8000c98: 46bd mov sp, r7
8000c9a: bd80 pop {r7, pc}
8000c9c: 40023800 .word 0x40023800
8000ca0: 40020000 .word 0x40020000
08000ca4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000ca4: b480 push {r7}
8000ca6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000ca8: bf00 nop
8000caa: e7fd b.n 8000ca8 <NMI_Handler+0x4>
08000cac <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000cac: b480 push {r7}
8000cae: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000cb0: bf00 nop
8000cb2: e7fd b.n 8000cb0 <HardFault_Handler+0x4>
08000cb4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000cb4: b480 push {r7}
8000cb6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000cb8: bf00 nop
8000cba: e7fd b.n 8000cb8 <MemManage_Handler+0x4>
08000cbc <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000cbc: b480 push {r7}
8000cbe: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000cc0: bf00 nop
8000cc2: e7fd b.n 8000cc0 <BusFault_Handler+0x4>
08000cc4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000cc4: b480 push {r7}
8000cc6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000cc8: bf00 nop
8000cca: e7fd b.n 8000cc8 <UsageFault_Handler+0x4>
08000ccc <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000ccc: b480 push {r7}
8000cce: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000cd0: bf00 nop
8000cd2: 46bd mov sp, r7
8000cd4: f85d 7b04 ldr.w r7, [sp], #4
8000cd8: 4770 bx lr
08000cda <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000cda: b480 push {r7}
8000cdc: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000cde: bf00 nop
8000ce0: 46bd mov sp, r7
8000ce2: f85d 7b04 ldr.w r7, [sp], #4
8000ce6: 4770 bx lr
08000ce8 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000ce8: b480 push {r7}
8000cea: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000cec: bf00 nop
8000cee: 46bd mov sp, r7
8000cf0: f85d 7b04 ldr.w r7, [sp], #4
8000cf4: 4770 bx lr
08000cf6 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000cf6: b580 push {r7, lr}
8000cf8: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000cfa: f000 f87b bl 8000df4 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000cfe: bf00 nop
8000d00: bd80 pop {r7, pc}
...
08000d04 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000d04: b480 push {r7}
8000d06: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000d08: 4b06 ldr r3, [pc, #24] @ (8000d24 <SystemInit+0x20>)
8000d0a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8000d0e: 4a05 ldr r2, [pc, #20] @ (8000d24 <SystemInit+0x20>)
8000d10: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8000d14: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000d18: bf00 nop
8000d1a: 46bd mov sp, r7
8000d1c: f85d 7b04 ldr.w r7, [sp], #4
8000d20: 4770 bx lr
8000d22: bf00 nop
8000d24: e000ed00 .word 0xe000ed00
08000d28 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000d28: f8df d034 ldr.w sp, [pc, #52] @ 8000d60 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8000d2c: f7ff ffea bl 8000d04 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000d30: 480c ldr r0, [pc, #48] @ (8000d64 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8000d32: 490d ldr r1, [pc, #52] @ (8000d68 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8000d34: 4a0d ldr r2, [pc, #52] @ (8000d6c <LoopFillZerobss+0x1a>)
movs r3, #0
8000d36: 2300 movs r3, #0
b LoopCopyDataInit
8000d38: e002 b.n 8000d40 <LoopCopyDataInit>
08000d3a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000d3a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000d3c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000d3e: 3304 adds r3, #4
08000d40 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000d40: 18c4 adds r4, r0, r3
cmp r4, r1
8000d42: 428c cmp r4, r1
bcc CopyDataInit
8000d44: d3f9 bcc.n 8000d3a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000d46: 4a0a ldr r2, [pc, #40] @ (8000d70 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8000d48: 4c0a ldr r4, [pc, #40] @ (8000d74 <LoopFillZerobss+0x22>)
movs r3, #0
8000d4a: 2300 movs r3, #0
b LoopFillZerobss
8000d4c: e001 b.n 8000d52 <LoopFillZerobss>
08000d4e <FillZerobss>:
FillZerobss:
str r3, [r2]
8000d4e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000d50: 3204 adds r2, #4
08000d52 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000d52: 42a2 cmp r2, r4
bcc FillZerobss
8000d54: d3fb bcc.n 8000d4e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000d56: f003 f907 bl 8003f68 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000d5a: f7ff fc03 bl 8000564 <main>
bx lr
8000d5e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000d60: 20080000 .word 0x20080000
ldr r0, =_sdata
8000d64: 20000000 .word 0x20000000
ldr r1, =_edata
8000d68: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000d6c: 08003ff0 .word 0x08003ff0
ldr r2, =_sbss
8000d70: 2000014c .word 0x2000014c
ldr r4, =_ebss
8000d74: 200007c4 .word 0x200007c4
08000d78 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000d78: e7fe b.n 8000d78 <ADC_IRQHandler>
08000d7a <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000d7a: b580 push {r7, lr}
8000d7c: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000d7e: 2003 movs r0, #3
8000d80: f000 f92e bl 8000fe0 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000d84: 2000 movs r0, #0
8000d86: f000 f805 bl 8000d94 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000d8a: f7ff fdd5 bl 8000938 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000d8e: 2300 movs r3, #0
}
8000d90: 4618 mov r0, r3
8000d92: bd80 pop {r7, pc}
08000d94 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000d94: b580 push {r7, lr}
8000d96: b082 sub sp, #8
8000d98: af00 add r7, sp, #0
8000d9a: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000d9c: 4b12 ldr r3, [pc, #72] @ (8000de8 <HAL_InitTick+0x54>)
8000d9e: 681a ldr r2, [r3, #0]
8000da0: 4b12 ldr r3, [pc, #72] @ (8000dec <HAL_InitTick+0x58>)
8000da2: 781b ldrb r3, [r3, #0]
8000da4: 4619 mov r1, r3
8000da6: f44f 737a mov.w r3, #1000 @ 0x3e8
8000daa: fbb3 f3f1 udiv r3, r3, r1
8000dae: fbb2 f3f3 udiv r3, r2, r3
8000db2: 4618 mov r0, r3
8000db4: f000 f93b bl 800102e <HAL_SYSTICK_Config>
8000db8: 4603 mov r3, r0
8000dba: 2b00 cmp r3, #0
8000dbc: d001 beq.n 8000dc2 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000dbe: 2301 movs r3, #1
8000dc0: e00e b.n 8000de0 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000dc2: 687b ldr r3, [r7, #4]
8000dc4: 2b0f cmp r3, #15
8000dc6: d80a bhi.n 8000dde <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000dc8: 2200 movs r2, #0
8000dca: 6879 ldr r1, [r7, #4]
8000dcc: f04f 30ff mov.w r0, #4294967295
8000dd0: f000 f911 bl 8000ff6 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000dd4: 4a06 ldr r2, [pc, #24] @ (8000df0 <HAL_InitTick+0x5c>)
8000dd6: 687b ldr r3, [r7, #4]
8000dd8: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000dda: 2300 movs r3, #0
8000ddc: e000 b.n 8000de0 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000dde: 2301 movs r3, #1
}
8000de0: 4618 mov r0, r3
8000de2: 3708 adds r7, #8
8000de4: 46bd mov sp, r7
8000de6: bd80 pop {r7, pc}
8000de8: 20000000 .word 0x20000000
8000dec: 20000008 .word 0x20000008
8000df0: 20000004 .word 0x20000004
08000df4 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000df4: b480 push {r7}
8000df6: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000df8: 4b06 ldr r3, [pc, #24] @ (8000e14 <HAL_IncTick+0x20>)
8000dfa: 781b ldrb r3, [r3, #0]
8000dfc: 461a mov r2, r3
8000dfe: 4b06 ldr r3, [pc, #24] @ (8000e18 <HAL_IncTick+0x24>)
8000e00: 681b ldr r3, [r3, #0]
8000e02: 4413 add r3, r2
8000e04: 4a04 ldr r2, [pc, #16] @ (8000e18 <HAL_IncTick+0x24>)
8000e06: 6013 str r3, [r2, #0]
}
8000e08: bf00 nop
8000e0a: 46bd mov sp, r7
8000e0c: f85d 7b04 ldr.w r7, [sp], #4
8000e10: 4770 bx lr
8000e12: bf00 nop
8000e14: 20000008 .word 0x20000008
8000e18: 200007c0 .word 0x200007c0
08000e1c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000e1c: b480 push {r7}
8000e1e: af00 add r7, sp, #0
return uwTick;
8000e20: 4b03 ldr r3, [pc, #12] @ (8000e30 <HAL_GetTick+0x14>)
8000e22: 681b ldr r3, [r3, #0]
}
8000e24: 4618 mov r0, r3
8000e26: 46bd mov sp, r7
8000e28: f85d 7b04 ldr.w r7, [sp], #4
8000e2c: 4770 bx lr
8000e2e: bf00 nop
8000e30: 200007c0 .word 0x200007c0
08000e34 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000e34: b580 push {r7, lr}
8000e36: b084 sub sp, #16
8000e38: af00 add r7, sp, #0
8000e3a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000e3c: f7ff ffee bl 8000e1c <HAL_GetTick>
8000e40: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000e42: 687b ldr r3, [r7, #4]
8000e44: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000e46: 68fb ldr r3, [r7, #12]
8000e48: f1b3 3fff cmp.w r3, #4294967295
8000e4c: d005 beq.n 8000e5a <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000e4e: 4b0a ldr r3, [pc, #40] @ (8000e78 <HAL_Delay+0x44>)
8000e50: 781b ldrb r3, [r3, #0]
8000e52: 461a mov r2, r3
8000e54: 68fb ldr r3, [r7, #12]
8000e56: 4413 add r3, r2
8000e58: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8000e5a: bf00 nop
8000e5c: f7ff ffde bl 8000e1c <HAL_GetTick>
8000e60: 4602 mov r2, r0
8000e62: 68bb ldr r3, [r7, #8]
8000e64: 1ad3 subs r3, r2, r3
8000e66: 68fa ldr r2, [r7, #12]
8000e68: 429a cmp r2, r3
8000e6a: d8f7 bhi.n 8000e5c <HAL_Delay+0x28>
{
}
}
8000e6c: bf00 nop
8000e6e: bf00 nop
8000e70: 3710 adds r7, #16
8000e72: 46bd mov sp, r7
8000e74: bd80 pop {r7, pc}
8000e76: bf00 nop
8000e78: 20000008 .word 0x20000008
08000e7c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000e7c: b480 push {r7}
8000e7e: b085 sub sp, #20
8000e80: af00 add r7, sp, #0
8000e82: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000e84: 687b ldr r3, [r7, #4]
8000e86: f003 0307 and.w r3, r3, #7
8000e8a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000e8c: 4b0b ldr r3, [pc, #44] @ (8000ebc <__NVIC_SetPriorityGrouping+0x40>)
8000e8e: 68db ldr r3, [r3, #12]
8000e90: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000e92: 68ba ldr r2, [r7, #8]
8000e94: f64f 03ff movw r3, #63743 @ 0xf8ff
8000e98: 4013 ands r3, r2
8000e9a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000e9c: 68fb ldr r3, [r7, #12]
8000e9e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000ea0: 68bb ldr r3, [r7, #8]
8000ea2: 431a orrs r2, r3
reg_value = (reg_value |
8000ea4: 4b06 ldr r3, [pc, #24] @ (8000ec0 <__NVIC_SetPriorityGrouping+0x44>)
8000ea6: 4313 orrs r3, r2
8000ea8: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000eaa: 4a04 ldr r2, [pc, #16] @ (8000ebc <__NVIC_SetPriorityGrouping+0x40>)
8000eac: 68bb ldr r3, [r7, #8]
8000eae: 60d3 str r3, [r2, #12]
}
8000eb0: bf00 nop
8000eb2: 3714 adds r7, #20
8000eb4: 46bd mov sp, r7
8000eb6: f85d 7b04 ldr.w r7, [sp], #4
8000eba: 4770 bx lr
8000ebc: e000ed00 .word 0xe000ed00
8000ec0: 05fa0000 .word 0x05fa0000
08000ec4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000ec4: b480 push {r7}
8000ec6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000ec8: 4b04 ldr r3, [pc, #16] @ (8000edc <__NVIC_GetPriorityGrouping+0x18>)
8000eca: 68db ldr r3, [r3, #12]
8000ecc: 0a1b lsrs r3, r3, #8
8000ece: f003 0307 and.w r3, r3, #7
}
8000ed2: 4618 mov r0, r3
8000ed4: 46bd mov sp, r7
8000ed6: f85d 7b04 ldr.w r7, [sp], #4
8000eda: 4770 bx lr
8000edc: e000ed00 .word 0xe000ed00
08000ee0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000ee0: b480 push {r7}
8000ee2: b083 sub sp, #12
8000ee4: af00 add r7, sp, #0
8000ee6: 4603 mov r3, r0
8000ee8: 6039 str r1, [r7, #0]
8000eea: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000eec: f997 3007 ldrsb.w r3, [r7, #7]
8000ef0: 2b00 cmp r3, #0
8000ef2: db0a blt.n 8000f0a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000ef4: 683b ldr r3, [r7, #0]
8000ef6: b2da uxtb r2, r3
8000ef8: 490c ldr r1, [pc, #48] @ (8000f2c <__NVIC_SetPriority+0x4c>)
8000efa: f997 3007 ldrsb.w r3, [r7, #7]
8000efe: 0112 lsls r2, r2, #4
8000f00: b2d2 uxtb r2, r2
8000f02: 440b add r3, r1
8000f04: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000f08: e00a b.n 8000f20 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000f0a: 683b ldr r3, [r7, #0]
8000f0c: b2da uxtb r2, r3
8000f0e: 4908 ldr r1, [pc, #32] @ (8000f30 <__NVIC_SetPriority+0x50>)
8000f10: 79fb ldrb r3, [r7, #7]
8000f12: f003 030f and.w r3, r3, #15
8000f16: 3b04 subs r3, #4
8000f18: 0112 lsls r2, r2, #4
8000f1a: b2d2 uxtb r2, r2
8000f1c: 440b add r3, r1
8000f1e: 761a strb r2, [r3, #24]
}
8000f20: bf00 nop
8000f22: 370c adds r7, #12
8000f24: 46bd mov sp, r7
8000f26: f85d 7b04 ldr.w r7, [sp], #4
8000f2a: 4770 bx lr
8000f2c: e000e100 .word 0xe000e100
8000f30: e000ed00 .word 0xe000ed00
08000f34 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000f34: b480 push {r7}
8000f36: b089 sub sp, #36 @ 0x24
8000f38: af00 add r7, sp, #0
8000f3a: 60f8 str r0, [r7, #12]
8000f3c: 60b9 str r1, [r7, #8]
8000f3e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000f40: 68fb ldr r3, [r7, #12]
8000f42: f003 0307 and.w r3, r3, #7
8000f46: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000f48: 69fb ldr r3, [r7, #28]
8000f4a: f1c3 0307 rsb r3, r3, #7
8000f4e: 2b04 cmp r3, #4
8000f50: bf28 it cs
8000f52: 2304 movcs r3, #4
8000f54: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000f56: 69fb ldr r3, [r7, #28]
8000f58: 3304 adds r3, #4
8000f5a: 2b06 cmp r3, #6
8000f5c: d902 bls.n 8000f64 <NVIC_EncodePriority+0x30>
8000f5e: 69fb ldr r3, [r7, #28]
8000f60: 3b03 subs r3, #3
8000f62: e000 b.n 8000f66 <NVIC_EncodePriority+0x32>
8000f64: 2300 movs r3, #0
8000f66: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000f68: f04f 32ff mov.w r2, #4294967295
8000f6c: 69bb ldr r3, [r7, #24]
8000f6e: fa02 f303 lsl.w r3, r2, r3
8000f72: 43da mvns r2, r3
8000f74: 68bb ldr r3, [r7, #8]
8000f76: 401a ands r2, r3
8000f78: 697b ldr r3, [r7, #20]
8000f7a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000f7c: f04f 31ff mov.w r1, #4294967295
8000f80: 697b ldr r3, [r7, #20]
8000f82: fa01 f303 lsl.w r3, r1, r3
8000f86: 43d9 mvns r1, r3
8000f88: 687b ldr r3, [r7, #4]
8000f8a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000f8c: 4313 orrs r3, r2
);
}
8000f8e: 4618 mov r0, r3
8000f90: 3724 adds r7, #36 @ 0x24
8000f92: 46bd mov sp, r7
8000f94: f85d 7b04 ldr.w r7, [sp], #4
8000f98: 4770 bx lr
...
08000f9c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000f9c: b580 push {r7, lr}
8000f9e: b082 sub sp, #8
8000fa0: af00 add r7, sp, #0
8000fa2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000fa4: 687b ldr r3, [r7, #4]
8000fa6: 3b01 subs r3, #1
8000fa8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8000fac: d301 bcc.n 8000fb2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000fae: 2301 movs r3, #1
8000fb0: e00f b.n 8000fd2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000fb2: 4a0a ldr r2, [pc, #40] @ (8000fdc <SysTick_Config+0x40>)
8000fb4: 687b ldr r3, [r7, #4]
8000fb6: 3b01 subs r3, #1
8000fb8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000fba: 210f movs r1, #15
8000fbc: f04f 30ff mov.w r0, #4294967295
8000fc0: f7ff ff8e bl 8000ee0 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000fc4: 4b05 ldr r3, [pc, #20] @ (8000fdc <SysTick_Config+0x40>)
8000fc6: 2200 movs r2, #0
8000fc8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000fca: 4b04 ldr r3, [pc, #16] @ (8000fdc <SysTick_Config+0x40>)
8000fcc: 2207 movs r2, #7
8000fce: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000fd0: 2300 movs r3, #0
}
8000fd2: 4618 mov r0, r3
8000fd4: 3708 adds r7, #8
8000fd6: 46bd mov sp, r7
8000fd8: bd80 pop {r7, pc}
8000fda: bf00 nop
8000fdc: e000e010 .word 0xe000e010
08000fe0 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000fe0: b580 push {r7, lr}
8000fe2: b082 sub sp, #8
8000fe4: af00 add r7, sp, #0
8000fe6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000fe8: 6878 ldr r0, [r7, #4]
8000fea: f7ff ff47 bl 8000e7c <__NVIC_SetPriorityGrouping>
}
8000fee: bf00 nop
8000ff0: 3708 adds r7, #8
8000ff2: 46bd mov sp, r7
8000ff4: bd80 pop {r7, pc}
08000ff6 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ff6: b580 push {r7, lr}
8000ff8: b086 sub sp, #24
8000ffa: af00 add r7, sp, #0
8000ffc: 4603 mov r3, r0
8000ffe: 60b9 str r1, [r7, #8]
8001000: 607a str r2, [r7, #4]
8001002: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8001004: 2300 movs r3, #0
8001006: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001008: f7ff ff5c bl 8000ec4 <__NVIC_GetPriorityGrouping>
800100c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800100e: 687a ldr r2, [r7, #4]
8001010: 68b9 ldr r1, [r7, #8]
8001012: 6978 ldr r0, [r7, #20]
8001014: f7ff ff8e bl 8000f34 <NVIC_EncodePriority>
8001018: 4602 mov r2, r0
800101a: f997 300f ldrsb.w r3, [r7, #15]
800101e: 4611 mov r1, r2
8001020: 4618 mov r0, r3
8001022: f7ff ff5d bl 8000ee0 <__NVIC_SetPriority>
}
8001026: bf00 nop
8001028: 3718 adds r7, #24
800102a: 46bd mov sp, r7
800102c: bd80 pop {r7, pc}
0800102e <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800102e: b580 push {r7, lr}
8001030: b082 sub sp, #8
8001032: af00 add r7, sp, #0
8001034: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001036: 6878 ldr r0, [r7, #4]
8001038: f7ff ffb0 bl 8000f9c <SysTick_Config>
800103c: 4603 mov r3, r0
}
800103e: 4618 mov r0, r3
8001040: 3708 adds r7, #8
8001042: 46bd mov sp, r7
8001044: bd80 pop {r7, pc}
...
08001048 <HAL_ETH_Init>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
8001048: b580 push {r7, lr}
800104a: b084 sub sp, #16
800104c: af00 add r7, sp, #0
800104e: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (heth == NULL)
8001050: 687b ldr r3, [r7, #4]
8001052: 2b00 cmp r3, #0
8001054: d101 bne.n 800105a <HAL_ETH_Init+0x12>
{
return HAL_ERROR;
8001056: 2301 movs r3, #1
8001058: e086 b.n 8001168 <HAL_ETH_Init+0x120>
}
if (heth->gState == HAL_ETH_STATE_RESET)
800105a: 687b ldr r3, [r7, #4]
800105c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8001060: 2b00 cmp r3, #0
8001062: d106 bne.n 8001072 <HAL_ETH_Init+0x2a>
{
heth->gState = HAL_ETH_STATE_BUSY;
8001064: 687b ldr r3, [r7, #4]
8001066: 2220 movs r2, #32
8001068: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init the low level hardware */
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
800106c: 6878 ldr r0, [r7, #4]
800106e: f7ff fc87 bl 8000980 <HAL_ETH_MspInit>
#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
}
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001072: 4b3f ldr r3, [pc, #252] @ (8001170 <HAL_ETH_Init+0x128>)
8001074: 6c5b ldr r3, [r3, #68] @ 0x44
8001076: 4a3e ldr r2, [pc, #248] @ (8001170 <HAL_ETH_Init+0x128>)
8001078: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800107c: 6453 str r3, [r2, #68] @ 0x44
800107e: 4b3c ldr r3, [pc, #240] @ (8001170 <HAL_ETH_Init+0x128>)
8001080: 6c5b ldr r3, [r3, #68] @ 0x44
8001082: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001086: 60bb str r3, [r7, #8]
8001088: 68bb ldr r3, [r7, #8]
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
800108a: 4b3a ldr r3, [pc, #232] @ (8001174 <HAL_ETH_Init+0x12c>)
800108c: 685b ldr r3, [r3, #4]
800108e: 4a39 ldr r2, [pc, #228] @ (8001174 <HAL_ETH_Init+0x12c>)
8001090: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
8001094: 6053 str r3, [r2, #4]
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
8001096: 4b37 ldr r3, [pc, #220] @ (8001174 <HAL_ETH_Init+0x12c>)
8001098: 685a ldr r2, [r3, #4]
800109a: 687b ldr r3, [r7, #4]
800109c: 689b ldr r3, [r3, #8]
800109e: 4935 ldr r1, [pc, #212] @ (8001174 <HAL_ETH_Init+0x12c>)
80010a0: 4313 orrs r3, r2
80010a2: 604b str r3, [r1, #4]
/* Dummy read to sync SYSCFG with ETH */
(void)SYSCFG->PMC;
80010a4: 4b33 ldr r3, [pc, #204] @ (8001174 <HAL_ETH_Init+0x12c>)
80010a6: 685b ldr r3, [r3, #4]
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR);
80010a8: 687b ldr r3, [r7, #4]
80010aa: 681b ldr r3, [r3, #0]
80010ac: f503 5380 add.w r3, r3, #4096 @ 0x1000
80010b0: 681b ldr r3, [r3, #0]
80010b2: 687a ldr r2, [r7, #4]
80010b4: 6812 ldr r2, [r2, #0]
80010b6: f043 0301 orr.w r3, r3, #1
80010ba: f502 5280 add.w r2, r2, #4096 @ 0x1000
80010be: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
80010c0: f7ff feac bl 8000e1c <HAL_GetTick>
80010c4: 60f8 str r0, [r7, #12]
/* Wait for software reset */
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
80010c6: e011 b.n 80010ec <HAL_ETH_Init+0xa4>
{
if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
80010c8: f7ff fea8 bl 8000e1c <HAL_GetTick>
80010cc: 4602 mov r2, r0
80010ce: 68fb ldr r3, [r7, #12]
80010d0: 1ad3 subs r3, r2, r3
80010d2: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
80010d6: d909 bls.n 80010ec <HAL_ETH_Init+0xa4>
{
/* Set Error Code */
heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
80010d8: 687b ldr r3, [r7, #4]
80010da: 2204 movs r2, #4
80010dc: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Set State as Error */
heth->gState = HAL_ETH_STATE_ERROR;
80010e0: 687b ldr r3, [r7, #4]
80010e2: 22e0 movs r2, #224 @ 0xe0
80010e4: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Return Error */
return HAL_ERROR;
80010e8: 2301 movs r3, #1
80010ea: e03d b.n 8001168 <HAL_ETH_Init+0x120>
while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
80010ec: 687b ldr r3, [r7, #4]
80010ee: 681b ldr r3, [r3, #0]
80010f0: f503 5380 add.w r3, r3, #4096 @ 0x1000
80010f4: 681b ldr r3, [r3, #0]
80010f6: f003 0301 and.w r3, r3, #1
80010fa: 2b00 cmp r3, #0
80010fc: d1e4 bne.n 80010c8 <HAL_ETH_Init+0x80>
}
}
/*------------------ MAC, MTL and DMA default Configuration ----------------*/
ETH_MACDMAConfig(heth);
80010fe: 6878 ldr r0, [r7, #4]
8001100: f000 f97a bl 80013f8 <ETH_MACDMAConfig>
/*------------------ DMA Tx Descriptors Configuration ----------------------*/
ETH_DMATxDescListInit(heth);
8001104: 6878 ldr r0, [r7, #4]
8001106: f000 fa25 bl 8001554 <ETH_DMATxDescListInit>
/*------------------ DMA Rx Descriptors Configuration ----------------------*/
ETH_DMARxDescListInit(heth);
800110a: 6878 ldr r0, [r7, #4]
800110c: f000 fa7b bl 8001606 <ETH_DMARxDescListInit>
/*--------------------- ETHERNET MAC Address Configuration ------------------*/
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
8001110: 687b ldr r3, [r7, #4]
8001112: 685b ldr r3, [r3, #4]
8001114: 461a mov r2, r3
8001116: 2100 movs r1, #0
8001118: 6878 ldr r0, [r7, #4]
800111a: f000 f9e3 bl 80014e4 <ETH_MACAddressConfig>
/* Disable MMC Interrupts */
SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM);
800111e: 687b ldr r3, [r7, #4]
8001120: 681b ldr r3, [r3, #0]
8001122: 6bda ldr r2, [r3, #60] @ 0x3c
8001124: 687b ldr r3, [r7, #4]
8001126: 681b ldr r3, [r3, #0]
8001128: f442 7202 orr.w r2, r2, #520 @ 0x208
800112c: 63da str r2, [r3, #60] @ 0x3c
/* Disable Rx MMC Interrupts */
SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \
800112e: 687b ldr r3, [r7, #4]
8001130: 681b ldr r3, [r3, #0]
8001132: f8d3 110c ldr.w r1, [r3, #268] @ 0x10c
8001136: 687b ldr r3, [r7, #4]
8001138: 681a ldr r2, [r3, #0]
800113a: 4b0f ldr r3, [pc, #60] @ (8001178 <HAL_ETH_Init+0x130>)
800113c: 430b orrs r3, r1
800113e: f8c2 310c str.w r3, [r2, #268] @ 0x10c
ETH_MMCRIMR_RFCEM);
/* Disable Tx MMC Interrupts */
SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \
8001142: 687b ldr r3, [r7, #4]
8001144: 681b ldr r3, [r3, #0]
8001146: f8d3 2110 ldr.w r2, [r3, #272] @ 0x110
800114a: 687b ldr r3, [r7, #4]
800114c: 681b ldr r3, [r3, #0]
800114e: f442 1203 orr.w r2, r2, #2146304 @ 0x20c000
8001152: f8c3 2110 str.w r2, [r3, #272] @ 0x110
ETH_MMCTIMR_TGFSCM);
heth->ErrorCode = HAL_ETH_ERROR_NONE;
8001156: 687b ldr r3, [r7, #4]
8001158: 2200 movs r2, #0
800115a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
heth->gState = HAL_ETH_STATE_READY;
800115e: 687b ldr r3, [r7, #4]
8001160: 2210 movs r2, #16
8001162: f8c3 2084 str.w r2, [r3, #132] @ 0x84
return HAL_OK;
8001166: 2300 movs r3, #0
}
8001168: 4618 mov r0, r3
800116a: 3710 adds r7, #16
800116c: 46bd mov sp, r7
800116e: bd80 pop {r7, pc}
8001170: 40023800 .word 0x40023800
8001174: 40013800 .word 0x40013800
8001178: 00020060 .word 0x00020060
0800117c <ETH_SetMACConfig>:
HAL_Delay(ETH_REG_WRITE_DELAY);
(heth->Instance)->DMAOMR = tmpreg;
}
static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
{
800117c: b580 push {r7, lr}
800117e: b084 sub sp, #16
8001180: af00 add r7, sp, #0
8001182: 6078 str r0, [r7, #4]
8001184: 6039 str r1, [r7, #0]
uint32_t tmpreg1;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg1 = (heth->Instance)->MACCR;
8001186: 687b ldr r3, [r7, #4]
8001188: 681b ldr r3, [r3, #0]
800118a: 681b ldr r3, [r3, #0]
800118c: 60fb str r3, [r7, #12]
/* Clear CSTF, WD, PCE, PS, TE and RE bits */
tmpreg1 &= ETH_MACCR_CLEAR_MASK;
800118e: 68fa ldr r2, [r7, #12]
8001190: 4b53 ldr r3, [pc, #332] @ (80012e0 <ETH_SetMACConfig+0x164>)
8001192: 4013 ands r3, r2
8001194: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
8001196: 683b ldr r3, [r7, #0]
8001198: 7b9b ldrb r3, [r3, #14]
800119a: 065b lsls r3, r3, #25
((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
800119c: 683a ldr r2, [r7, #0]
800119e: 7c12 ldrb r2, [r2, #16]
80011a0: 2a00 cmp r2, #0
80011a2: d102 bne.n 80011aa <ETH_SetMACConfig+0x2e>
80011a4: f44f 0200 mov.w r2, #8388608 @ 0x800000
80011a8: e000 b.n 80011ac <ETH_SetMACConfig+0x30>
80011aa: 2200 movs r2, #0
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
80011ac: 4313 orrs r3, r2
((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
80011ae: 683a ldr r2, [r7, #0]
80011b0: 7c52 ldrb r2, [r2, #17]
80011b2: 2a00 cmp r2, #0
80011b4: d102 bne.n 80011bc <ETH_SetMACConfig+0x40>
80011b6: f44f 0280 mov.w r2, #4194304 @ 0x400000
80011ba: e000 b.n 80011be <ETH_SetMACConfig+0x42>
80011bc: 2200 movs r2, #0
((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
80011be: 431a orrs r2, r3
(uint32_t)macconf->InterPacketGapVal |
80011c0: 683b ldr r3, [r7, #0]
80011c2: 689b ldr r3, [r3, #8]
((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
80011c4: 431a orrs r2, r3
((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
80011c6: 683b ldr r3, [r7, #0]
80011c8: 7fdb ldrb r3, [r3, #31]
80011ca: 041b lsls r3, r3, #16
(uint32_t)macconf->InterPacketGapVal |
80011cc: 431a orrs r2, r3
macconf->Speed |
80011ce: 683b ldr r3, [r7, #0]
80011d0: 695b ldr r3, [r3, #20]
((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
80011d2: 4313 orrs r3, r2
((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) |
80011d4: 683a ldr r2, [r7, #0]
80011d6: 7f92 ldrb r2, [r2, #30]
80011d8: 2a00 cmp r2, #0
80011da: d102 bne.n 80011e2 <ETH_SetMACConfig+0x66>
80011dc: f44f 5200 mov.w r2, #8192 @ 0x2000
80011e0: e000 b.n 80011e4 <ETH_SetMACConfig+0x68>
80011e2: 2200 movs r2, #0
macconf->Speed |
80011e4: 431a orrs r2, r3
((uint32_t)macconf->LoopbackMode << 12U) |
80011e6: 683b ldr r3, [r7, #0]
80011e8: 7f1b ldrb r3, [r3, #28]
80011ea: 031b lsls r3, r3, #12
((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) |
80011ec: 431a orrs r2, r3
macconf->DuplexMode |
80011ee: 683b ldr r3, [r7, #0]
80011f0: 699b ldr r3, [r3, #24]
((uint32_t)macconf->LoopbackMode << 12U) |
80011f2: 431a orrs r2, r3
((uint32_t)macconf->ChecksumOffload << 10U) |
80011f4: 683b ldr r3, [r7, #0]
80011f6: 791b ldrb r3, [r3, #4]
80011f8: 029b lsls r3, r3, #10
macconf->DuplexMode |
80011fa: 4313 orrs r3, r2
((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) |
80011fc: 683a ldr r2, [r7, #0]
80011fe: f892 2020 ldrb.w r2, [r2, #32]
8001202: 2a00 cmp r2, #0
8001204: d102 bne.n 800120c <ETH_SetMACConfig+0x90>
8001206: f44f 7200 mov.w r2, #512 @ 0x200
800120a: e000 b.n 800120e <ETH_SetMACConfig+0x92>
800120c: 2200 movs r2, #0
((uint32_t)macconf->ChecksumOffload << 10U) |
800120e: 431a orrs r2, r3
((uint32_t)macconf->AutomaticPadCRCStrip << 7U) |
8001210: 683b ldr r3, [r7, #0]
8001212: 7bdb ldrb r3, [r3, #15]
8001214: 01db lsls r3, r3, #7
((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) |
8001216: 431a orrs r2, r3
macconf->BackOffLimit |
8001218: 683b ldr r3, [r7, #0]
800121a: 6a5b ldr r3, [r3, #36] @ 0x24
((uint32_t)macconf->AutomaticPadCRCStrip << 7U) |
800121c: 431a orrs r2, r3
((uint32_t)macconf->DeferralCheck << 4U));
800121e: 683b ldr r3, [r7, #0]
8001220: f893 3028 ldrb.w r3, [r3, #40] @ 0x28
8001224: 011b lsls r3, r3, #4
tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
8001226: 4313 orrs r3, r2
8001228: 68fa ldr r2, [r7, #12]
800122a: 4313 orrs r3, r2
800122c: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg1;
800122e: 687b ldr r3, [r7, #4]
8001230: 681b ldr r3, [r3, #0]
8001232: 68fa ldr r2, [r7, #12]
8001234: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACCR;
8001236: 687b ldr r3, [r7, #4]
8001238: 681b ldr r3, [r3, #0]
800123a: 681b ldr r3, [r3, #0]
800123c: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
800123e: 2001 movs r0, #1
8001240: f7ff fdf8 bl 8000e34 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg1;
8001244: 687b ldr r3, [r7, #4]
8001246: 681b ldr r3, [r3, #0]
8001248: 68fa ldr r2, [r7, #12]
800124a: 601a str r2, [r3, #0]
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg1 = (heth->Instance)->MACFCR;
800124c: 687b ldr r3, [r7, #4]
800124e: 681b ldr r3, [r3, #0]
8001250: 699b ldr r3, [r3, #24]
8001252: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
8001254: 68fa ldr r2, [r7, #12]
8001256: f64f 7341 movw r3, #65345 @ 0xff41
800125a: 4013 ands r3, r2
800125c: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
800125e: 683b ldr r3, [r7, #0]
8001260: 6c9b ldr r3, [r3, #72] @ 0x48
8001262: 041b lsls r3, r3, #16
((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) |
8001264: 683a ldr r2, [r7, #0]
8001266: f892 204c ldrb.w r2, [r2, #76] @ 0x4c
800126a: 2a00 cmp r2, #0
800126c: d101 bne.n 8001272 <ETH_SetMACConfig+0xf6>
800126e: 2280 movs r2, #128 @ 0x80
8001270: e000 b.n 8001274 <ETH_SetMACConfig+0xf8>
8001272: 2200 movs r2, #0
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
8001274: 431a orrs r2, r3
macconf->PauseLowThreshold |
8001276: 683b ldr r3, [r7, #0]
8001278: 6d1b ldr r3, [r3, #80] @ 0x50
((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) |
800127a: 4313 orrs r3, r2
((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) |
800127c: 683a ldr r2, [r7, #0]
800127e: f892 2055 ldrb.w r2, [r2, #85] @ 0x55
8001282: 2a01 cmp r2, #1
8001284: d101 bne.n 800128a <ETH_SetMACConfig+0x10e>
8001286: 2208 movs r2, #8
8001288: e000 b.n 800128c <ETH_SetMACConfig+0x110>
800128a: 2200 movs r2, #0
macconf->PauseLowThreshold |
800128c: 4313 orrs r3, r2
((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) |
800128e: 683a ldr r2, [r7, #0]
8001290: f892 2056 ldrb.w r2, [r2, #86] @ 0x56
8001294: 2a01 cmp r2, #1
8001296: d101 bne.n 800129c <ETH_SetMACConfig+0x120>
8001298: 2204 movs r2, #4
800129a: e000 b.n 800129e <ETH_SetMACConfig+0x122>
800129c: 2200 movs r2, #0
((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) |
800129e: 4313 orrs r3, r2
((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U));
80012a0: 683a ldr r2, [r7, #0]
80012a2: f892 2054 ldrb.w r2, [r2, #84] @ 0x54
80012a6: 2a01 cmp r2, #1
80012a8: d101 bne.n 80012ae <ETH_SetMACConfig+0x132>
80012aa: 2202 movs r2, #2
80012ac: e000 b.n 80012b0 <ETH_SetMACConfig+0x134>
80012ae: 2200 movs r2, #0
tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
80012b0: 4313 orrs r3, r2
80012b2: 68fa ldr r2, [r7, #12]
80012b4: 4313 orrs r3, r2
80012b6: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg1;
80012b8: 687b ldr r3, [r7, #4]
80012ba: 681b ldr r3, [r3, #0]
80012bc: 68fa ldr r2, [r7, #12]
80012be: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->MACFCR;
80012c0: 687b ldr r3, [r7, #4]
80012c2: 681b ldr r3, [r3, #0]
80012c4: 699b ldr r3, [r3, #24]
80012c6: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80012c8: 2001 movs r0, #1
80012ca: f7ff fdb3 bl 8000e34 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg1;
80012ce: 687b ldr r3, [r7, #4]
80012d0: 681b ldr r3, [r3, #0]
80012d2: 68fa ldr r2, [r7, #12]
80012d4: 619a str r2, [r3, #24]
}
80012d6: bf00 nop
80012d8: 3710 adds r7, #16
80012da: 46bd mov sp, r7
80012dc: bd80 pop {r7, pc}
80012de: bf00 nop
80012e0: fd20810f .word 0xfd20810f
080012e4 <ETH_SetDMAConfig>:
static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
{
80012e4: b580 push {r7, lr}
80012e6: b084 sub sp, #16
80012e8: af00 add r7, sp, #0
80012ea: 6078 str r0, [r7, #4]
80012ec: 6039 str r1, [r7, #0]
uint32_t tmpreg1;
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
tmpreg1 = (heth->Instance)->DMAOMR;
80012ee: 687b ldr r3, [r7, #4]
80012f0: 681b ldr r3, [r3, #0]
80012f2: f503 5380 add.w r3, r3, #4096 @ 0x1000
80012f6: 699b ldr r3, [r3, #24]
80012f8: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
80012fa: 68fa ldr r2, [r7, #12]
80012fc: 4b3d ldr r3, [pc, #244] @ (80013f4 <ETH_SetDMAConfig+0x110>)
80012fe: 4013 ands r3, r2
8001300: 60fb str r3, [r7, #12]
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
8001302: 683b ldr r3, [r7, #0]
8001304: 7b1b ldrb r3, [r3, #12]
8001306: 2b00 cmp r3, #0
8001308: d102 bne.n 8001310 <ETH_SetDMAConfig+0x2c>
800130a: f04f 6280 mov.w r2, #67108864 @ 0x4000000
800130e: e000 b.n 8001312 <ETH_SetDMAConfig+0x2e>
8001310: 2200 movs r2, #0
((uint32_t)dmaconf->ReceiveStoreForward << 25U) |
8001312: 683b ldr r3, [r7, #0]
8001314: 7b5b ldrb r3, [r3, #13]
8001316: 065b lsls r3, r3, #25
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
8001318: 4313 orrs r3, r2
((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) |
800131a: 683a ldr r2, [r7, #0]
800131c: 7f52 ldrb r2, [r2, #29]
800131e: 2a00 cmp r2, #0
8001320: d102 bne.n 8001328 <ETH_SetDMAConfig+0x44>
8001322: f44f 1280 mov.w r2, #1048576 @ 0x100000
8001326: e000 b.n 800132a <ETH_SetDMAConfig+0x46>
8001328: 2200 movs r2, #0
((uint32_t)dmaconf->ReceiveStoreForward << 25U) |
800132a: 431a orrs r2, r3
((uint32_t)dmaconf->TransmitStoreForward << 21U) |
800132c: 683b ldr r3, [r7, #0]
800132e: 7b9b ldrb r3, [r3, #14]
8001330: 055b lsls r3, r3, #21
((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) |
8001332: 431a orrs r2, r3
dmaconf->TransmitThresholdControl |
8001334: 683b ldr r3, [r7, #0]
8001336: 695b ldr r3, [r3, #20]
((uint32_t)dmaconf->TransmitStoreForward << 21U) |
8001338: 431a orrs r2, r3
((uint32_t)dmaconf->ForwardErrorFrames << 7U) |
800133a: 683b ldr r3, [r7, #0]
800133c: 7f1b ldrb r3, [r3, #28]
800133e: 01db lsls r3, r3, #7
dmaconf->TransmitThresholdControl |
8001340: 431a orrs r2, r3
((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) |
8001342: 683b ldr r3, [r7, #0]
8001344: 7f9b ldrb r3, [r3, #30]
8001346: 019b lsls r3, r3, #6
((uint32_t)dmaconf->ForwardErrorFrames << 7U) |
8001348: 431a orrs r2, r3
dmaconf->ReceiveThresholdControl |
800134a: 683b ldr r3, [r7, #0]
800134c: 6a1b ldr r3, [r3, #32]
((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) |
800134e: 431a orrs r2, r3
((uint32_t)dmaconf->SecondFrameOperate << 2U));
8001350: 683b ldr r3, [r7, #0]
8001352: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001356: 009b lsls r3, r3, #2
tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
8001358: 4313 orrs r3, r2
800135a: 68fa ldr r2, [r7, #12]
800135c: 4313 orrs r3, r2
800135e: 60fb str r3, [r7, #12]
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
8001360: 687b ldr r3, [r7, #4]
8001362: 681b ldr r3, [r3, #0]
8001364: f503 5380 add.w r3, r3, #4096 @ 0x1000
8001368: 461a mov r2, r3
800136a: 68fb ldr r3, [r7, #12]
800136c: 6193 str r3, [r2, #24]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMAOMR;
800136e: 687b ldr r3, [r7, #4]
8001370: 681b ldr r3, [r3, #0]
8001372: f503 5380 add.w r3, r3, #4096 @ 0x1000
8001376: 699b ldr r3, [r3, #24]
8001378: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
800137a: 2001 movs r0, #1
800137c: f7ff fd5a bl 8000e34 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg1;
8001380: 687b ldr r3, [r7, #4]
8001382: 681b ldr r3, [r3, #0]
8001384: f503 5380 add.w r3, r3, #4096 @ 0x1000
8001388: 461a mov r2, r3
800138a: 68fb ldr r3, [r7, #12]
800138c: 6193 str r3, [r2, #24]
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
800138e: 683b ldr r3, [r7, #0]
8001390: 791b ldrb r3, [r3, #4]
8001392: 065a lsls r2, r3, #25
dmaconf->BurstMode |
8001394: 683b ldr r3, [r7, #0]
8001396: 689b ldr r3, [r3, #8]
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
8001398: 431a orrs r2, r3
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or
800139a: 683b ldr r3, [r7, #0]
800139c: 699b ldr r3, [r3, #24]
dmaconf->BurstMode |
800139e: 431a orrs r2, r3
Rx it is applied for the other */
dmaconf->TxDMABurstLength |
80013a0: 683b ldr r3, [r7, #0]
80013a2: 691b ldr r3, [r3, #16]
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or
80013a4: 431a orrs r2, r3
((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) |
80013a6: 683b ldr r3, [r7, #0]
80013a8: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
80013ac: 01db lsls r3, r3, #7
dmaconf->TxDMABurstLength |
80013ae: 431a orrs r2, r3
(dmaconf->DescriptorSkipLength << 2U) |
80013b0: 683b ldr r3, [r7, #0]
80013b2: 6a9b ldr r3, [r3, #40] @ 0x28
80013b4: 009b lsls r3, r3, #2
((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) |
80013b6: 431a orrs r2, r3
dmaconf->DMAArbitration |
80013b8: 683b ldr r3, [r7, #0]
80013ba: 681b ldr r3, [r3, #0]
(dmaconf->DescriptorSkipLength << 2U) |
80013bc: 4313 orrs r3, r2
(heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
80013be: 687a ldr r2, [r7, #4]
80013c0: 6812 ldr r2, [r2, #0]
80013c2: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
80013c6: f502 5280 add.w r2, r2, #4096 @ 0x1000
80013ca: 6013 str r3, [r2, #0]
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg1 = (heth->Instance)->DMABMR;
80013cc: 687b ldr r3, [r7, #4]
80013ce: 681b ldr r3, [r3, #0]
80013d0: f503 5380 add.w r3, r3, #4096 @ 0x1000
80013d4: 681b ldr r3, [r3, #0]
80013d6: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80013d8: 2001 movs r0, #1
80013da: f7ff fd2b bl 8000e34 <HAL_Delay>
(heth->Instance)->DMABMR = tmpreg1;
80013de: 687b ldr r3, [r7, #4]
80013e0: 681b ldr r3, [r3, #0]
80013e2: f503 5380 add.w r3, r3, #4096 @ 0x1000
80013e6: 461a mov r2, r3
80013e8: 68fb ldr r3, [r7, #12]
80013ea: 6013 str r3, [r2, #0]
}
80013ec: bf00 nop
80013ee: 3710 adds r7, #16
80013f0: 46bd mov sp, r7
80013f2: bd80 pop {r7, pc}
80013f4: f8de3f23 .word 0xf8de3f23
080013f8 <ETH_MACDMAConfig>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
{
80013f8: b580 push {r7, lr}
80013fa: b0a6 sub sp, #152 @ 0x98
80013fc: af00 add r7, sp, #0
80013fe: 6078 str r0, [r7, #4]
ETH_MACConfigTypeDef macDefaultConf;
ETH_DMAConfigTypeDef dmaDefaultConf;
/*--------------- ETHERNET MAC registers default Configuration --------------*/
macDefaultConf.Watchdog = ENABLE;
8001400: 2301 movs r3, #1
8001402: f887 3044 strb.w r3, [r7, #68] @ 0x44
macDefaultConf.Jabber = ENABLE;
8001406: 2301 movs r3, #1
8001408: f887 3045 strb.w r3, [r7, #69] @ 0x45
macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT;
800140c: 2300 movs r3, #0
800140e: 63fb str r3, [r7, #60] @ 0x3c
macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
8001410: 2300 movs r3, #0
8001412: f887 3053 strb.w r3, [r7, #83] @ 0x53
macDefaultConf.ReceiveOwn = ENABLE;
8001416: 2301 movs r3, #1
8001418: f887 3052 strb.w r3, [r7, #82] @ 0x52
macDefaultConf.LoopbackMode = DISABLE;
800141c: 2300 movs r3, #0
800141e: f887 3050 strb.w r3, [r7, #80] @ 0x50
macDefaultConf.CRCStripTypePacket = ENABLE;
8001422: 2301 movs r3, #1
8001424: f887 3042 strb.w r3, [r7, #66] @ 0x42
macDefaultConf.ChecksumOffload = ENABLE;
8001428: 2301 movs r3, #1
800142a: f887 3038 strb.w r3, [r7, #56] @ 0x38
macDefaultConf.RetryTransmission = DISABLE;
800142e: 2300 movs r3, #0
8001430: f887 3054 strb.w r3, [r7, #84] @ 0x54
macDefaultConf.AutomaticPadCRCStrip = DISABLE;
8001434: 2300 movs r3, #0
8001436: f887 3043 strb.w r3, [r7, #67] @ 0x43
macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
800143a: 2300 movs r3, #0
800143c: 65bb str r3, [r7, #88] @ 0x58
macDefaultConf.DeferralCheck = DISABLE;
800143e: 2300 movs r3, #0
8001440: f887 305c strb.w r3, [r7, #92] @ 0x5c
macDefaultConf.PauseTime = 0x0U;
8001444: 2300 movs r3, #0
8001446: 67fb str r3, [r7, #124] @ 0x7c
macDefaultConf.ZeroQuantaPause = DISABLE;
8001448: 2300 movs r3, #0
800144a: f887 3080 strb.w r3, [r7, #128] @ 0x80
macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
800144e: 2300 movs r3, #0
8001450: f8c7 3084 str.w r3, [r7, #132] @ 0x84
macDefaultConf.ReceiveFlowControl = DISABLE;
8001454: 2300 movs r3, #0
8001456: f887 308a strb.w r3, [r7, #138] @ 0x8a
macDefaultConf.TransmitFlowControl = DISABLE;
800145a: 2300 movs r3, #0
800145c: f887 3088 strb.w r3, [r7, #136] @ 0x88
macDefaultConf.Speed = ETH_SPEED_100M;
8001460: f44f 4380 mov.w r3, #16384 @ 0x4000
8001464: 64bb str r3, [r7, #72] @ 0x48
macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
8001466: f44f 6300 mov.w r3, #2048 @ 0x800
800146a: 64fb str r3, [r7, #76] @ 0x4c
macDefaultConf.UnicastPausePacketDetect = DISABLE;
800146c: 2300 movs r3, #0
800146e: f887 3089 strb.w r3, [r7, #137] @ 0x89
/* MAC default configuration */
ETH_SetMACConfig(heth, &macDefaultConf);
8001472: f107 0334 add.w r3, r7, #52 @ 0x34
8001476: 4619 mov r1, r3
8001478: 6878 ldr r0, [r7, #4]
800147a: f7ff fe7f bl 800117c <ETH_SetMACConfig>
/*--------------- ETHERNET DMA registers default Configuration --------------*/
dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE;
800147e: 2301 movs r3, #1
8001480: 753b strb r3, [r7, #20]
dmaDefaultConf.ReceiveStoreForward = ENABLE;
8001482: 2301 movs r3, #1
8001484: 757b strb r3, [r7, #21]
dmaDefaultConf.FlushRxPacket = ENABLE;
8001486: 2301 movs r3, #1
8001488: f887 3025 strb.w r3, [r7, #37] @ 0x25
dmaDefaultConf.TransmitStoreForward = ENABLE;
800148c: 2301 movs r3, #1
800148e: 75bb strb r3, [r7, #22]
dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
8001490: 2300 movs r3, #0
8001492: 61fb str r3, [r7, #28]
dmaDefaultConf.ForwardErrorFrames = DISABLE;
8001494: 2300 movs r3, #0
8001496: f887 3024 strb.w r3, [r7, #36] @ 0x24
dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE;
800149a: 2300 movs r3, #0
800149c: f887 3026 strb.w r3, [r7, #38] @ 0x26
dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
80014a0: 2300 movs r3, #0
80014a2: 62bb str r3, [r7, #40] @ 0x28
dmaDefaultConf.SecondFrameOperate = ENABLE;
80014a4: 2301 movs r3, #1
80014a6: f887 302c strb.w r3, [r7, #44] @ 0x2c
dmaDefaultConf.AddressAlignedBeats = ENABLE;
80014aa: 2301 movs r3, #1
80014ac: 733b strb r3, [r7, #12]
dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
80014ae: f44f 3380 mov.w r3, #65536 @ 0x10000
80014b2: 613b str r3, [r7, #16]
dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
80014b4: f44f 0380 mov.w r3, #4194304 @ 0x400000
80014b8: 623b str r3, [r7, #32]
dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
80014ba: f44f 5300 mov.w r3, #8192 @ 0x2000
80014be: 61bb str r3, [r7, #24]
dmaDefaultConf.EnhancedDescriptorFormat = ENABLE;
80014c0: 2301 movs r3, #1
80014c2: f887 302d strb.w r3, [r7, #45] @ 0x2d
dmaDefaultConf.DescriptorSkipLength = 0x0U;
80014c6: 2300 movs r3, #0
80014c8: 633b str r3, [r7, #48] @ 0x30
dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
80014ca: 2300 movs r3, #0
80014cc: 60bb str r3, [r7, #8]
/* DMA default configuration */
ETH_SetDMAConfig(heth, &dmaDefaultConf);
80014ce: f107 0308 add.w r3, r7, #8
80014d2: 4619 mov r1, r3
80014d4: 6878 ldr r0, [r7, #4]
80014d6: f7ff ff05 bl 80012e4 <ETH_SetDMAConfig>
}
80014da: bf00 nop
80014dc: 3798 adds r7, #152 @ 0x98
80014de: 46bd mov sp, r7
80014e0: bd80 pop {r7, pc}
...
080014e4 <ETH_MACAddressConfig>:
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
80014e4: b480 push {r7}
80014e6: b087 sub sp, #28
80014e8: af00 add r7, sp, #0
80014ea: 60f8 str r0, [r7, #12]
80014ec: 60b9 str r1, [r7, #8]
80014ee: 607a str r2, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(heth);
/* Calculate the selected MAC address high register */
tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
80014f0: 687b ldr r3, [r7, #4]
80014f2: 3305 adds r3, #5
80014f4: 781b ldrb r3, [r3, #0]
80014f6: 021b lsls r3, r3, #8
80014f8: 687a ldr r2, [r7, #4]
80014fa: 3204 adds r2, #4
80014fc: 7812 ldrb r2, [r2, #0]
80014fe: 4313 orrs r3, r2
8001500: 617b str r3, [r7, #20]
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
8001502: 68ba ldr r2, [r7, #8]
8001504: 4b11 ldr r3, [pc, #68] @ (800154c <ETH_MACAddressConfig+0x68>)
8001506: 4413 add r3, r2
8001508: 461a mov r2, r3
800150a: 697b ldr r3, [r7, #20]
800150c: 6013 str r3, [r2, #0]
/* Calculate the selected MAC address low register */
tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
800150e: 687b ldr r3, [r7, #4]
8001510: 3303 adds r3, #3
8001512: 781b ldrb r3, [r3, #0]
8001514: 061a lsls r2, r3, #24
8001516: 687b ldr r3, [r7, #4]
8001518: 3302 adds r3, #2
800151a: 781b ldrb r3, [r3, #0]
800151c: 041b lsls r3, r3, #16
800151e: 431a orrs r2, r3
8001520: 687b ldr r3, [r7, #4]
8001522: 3301 adds r3, #1
8001524: 781b ldrb r3, [r3, #0]
8001526: 021b lsls r3, r3, #8
8001528: 4313 orrs r3, r2
800152a: 687a ldr r2, [r7, #4]
800152c: 7812 ldrb r2, [r2, #0]
800152e: 4313 orrs r3, r2
8001530: 617b str r3, [r7, #20]
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
8001532: 68ba ldr r2, [r7, #8]
8001534: 4b06 ldr r3, [pc, #24] @ (8001550 <ETH_MACAddressConfig+0x6c>)
8001536: 4413 add r3, r2
8001538: 461a mov r2, r3
800153a: 697b ldr r3, [r7, #20]
800153c: 6013 str r3, [r2, #0]
}
800153e: bf00 nop
8001540: 371c adds r7, #28
8001542: 46bd mov sp, r7
8001544: f85d 7b04 ldr.w r7, [sp], #4
8001548: 4770 bx lr
800154a: bf00 nop
800154c: 40028040 .word 0x40028040
8001550: 40028044 .word 0x40028044
08001554 <ETH_DMATxDescListInit>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
{
8001554: b480 push {r7}
8001556: b085 sub sp, #20
8001558: af00 add r7, sp, #0
800155a: 6078 str r0, [r7, #4]
ETH_DMADescTypeDef *dmatxdesc;
uint32_t i;
/* Fill each DMATxDesc descriptor with the right values */
for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
800155c: 2300 movs r3, #0
800155e: 60fb str r3, [r7, #12]
8001560: e03e b.n 80015e0 <ETH_DMATxDescListInit+0x8c>
{
dmatxdesc = heth->Init.TxDesc + i;
8001562: 687b ldr r3, [r7, #4]
8001564: 68d9 ldr r1, [r3, #12]
8001566: 68fa ldr r2, [r7, #12]
8001568: 4613 mov r3, r2
800156a: 009b lsls r3, r3, #2
800156c: 4413 add r3, r2
800156e: 00db lsls r3, r3, #3
8001570: 440b add r3, r1
8001572: 60bb str r3, [r7, #8]
WRITE_REG(dmatxdesc->DESC0, 0x0U);
8001574: 68bb ldr r3, [r7, #8]
8001576: 2200 movs r2, #0
8001578: 601a str r2, [r3, #0]
WRITE_REG(dmatxdesc->DESC1, 0x0U);
800157a: 68bb ldr r3, [r7, #8]
800157c: 2200 movs r2, #0
800157e: 605a str r2, [r3, #4]
WRITE_REG(dmatxdesc->DESC2, 0x0U);
8001580: 68bb ldr r3, [r7, #8]
8001582: 2200 movs r2, #0
8001584: 609a str r2, [r3, #8]
WRITE_REG(dmatxdesc->DESC3, 0x0U);
8001586: 68bb ldr r3, [r7, #8]
8001588: 2200 movs r2, #0
800158a: 60da str r2, [r3, #12]
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
800158c: 68b9 ldr r1, [r7, #8]
800158e: 687b ldr r3, [r7, #4]
8001590: 68fa ldr r2, [r7, #12]
8001592: 3206 adds r2, #6
8001594: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Set Second Address Chained bit */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH);
8001598: 68bb ldr r3, [r7, #8]
800159a: 681b ldr r3, [r3, #0]
800159c: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
80015a0: 68bb ldr r3, [r7, #8]
80015a2: 601a str r2, [r3, #0]
if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U))
80015a4: 68fb ldr r3, [r7, #12]
80015a6: 2b02 cmp r3, #2
80015a8: d80c bhi.n 80015c4 <ETH_DMATxDescListInit+0x70>
{
WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U));
80015aa: 687b ldr r3, [r7, #4]
80015ac: 68d9 ldr r1, [r3, #12]
80015ae: 68fb ldr r3, [r7, #12]
80015b0: 1c5a adds r2, r3, #1
80015b2: 4613 mov r3, r2
80015b4: 009b lsls r3, r3, #2
80015b6: 4413 add r3, r2
80015b8: 00db lsls r3, r3, #3
80015ba: 440b add r3, r1
80015bc: 461a mov r2, r3
80015be: 68bb ldr r3, [r7, #8]
80015c0: 60da str r2, [r3, #12]
80015c2: e004 b.n 80015ce <ETH_DMATxDescListInit+0x7a>
}
else
{
WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc));
80015c4: 687b ldr r3, [r7, #4]
80015c6: 68db ldr r3, [r3, #12]
80015c8: 461a mov r2, r3
80015ca: 68bb ldr r3, [r7, #8]
80015cc: 60da str r2, [r3, #12]
}
/* Set the DMA Tx descriptors checksum insertion */
SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL);
80015ce: 68bb ldr r3, [r7, #8]
80015d0: 681b ldr r3, [r3, #0]
80015d2: f443 0240 orr.w r2, r3, #12582912 @ 0xc00000
80015d6: 68bb ldr r3, [r7, #8]
80015d8: 601a str r2, [r3, #0]
for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
80015da: 68fb ldr r3, [r7, #12]
80015dc: 3301 adds r3, #1
80015de: 60fb str r3, [r7, #12]
80015e0: 68fb ldr r3, [r7, #12]
80015e2: 2b03 cmp r3, #3
80015e4: d9bd bls.n 8001562 <ETH_DMATxDescListInit+0xe>
}
heth->TxDescList.CurTxDesc = 0;
80015e6: 687b ldr r3, [r7, #4]
80015e8: 2200 movs r2, #0
80015ea: 629a str r2, [r3, #40] @ 0x28
/* Set Transmit Descriptor List Address */
WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc);
80015ec: 687b ldr r3, [r7, #4]
80015ee: 68da ldr r2, [r3, #12]
80015f0: 687b ldr r3, [r7, #4]
80015f2: 681b ldr r3, [r3, #0]
80015f4: f503 5380 add.w r3, r3, #4096 @ 0x1000
80015f8: 611a str r2, [r3, #16]
}
80015fa: bf00 nop
80015fc: 3714 adds r7, #20
80015fe: 46bd mov sp, r7
8001600: f85d 7b04 ldr.w r7, [sp], #4
8001604: 4770 bx lr
08001606 <ETH_DMARxDescListInit>:
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
{
8001606: b480 push {r7}
8001608: b085 sub sp, #20
800160a: af00 add r7, sp, #0
800160c: 6078 str r0, [r7, #4]
ETH_DMADescTypeDef *dmarxdesc;
uint32_t i;
for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
800160e: 2300 movs r3, #0
8001610: 60fb str r3, [r7, #12]
8001612: e048 b.n 80016a6 <ETH_DMARxDescListInit+0xa0>
{
dmarxdesc = heth->Init.RxDesc + i;
8001614: 687b ldr r3, [r7, #4]
8001616: 6919 ldr r1, [r3, #16]
8001618: 68fa ldr r2, [r7, #12]
800161a: 4613 mov r3, r2
800161c: 009b lsls r3, r3, #2
800161e: 4413 add r3, r2
8001620: 00db lsls r3, r3, #3
8001622: 440b add r3, r1
8001624: 60bb str r3, [r7, #8]
WRITE_REG(dmarxdesc->DESC0, 0x0U);
8001626: 68bb ldr r3, [r7, #8]
8001628: 2200 movs r2, #0
800162a: 601a str r2, [r3, #0]
WRITE_REG(dmarxdesc->DESC1, 0x0U);
800162c: 68bb ldr r3, [r7, #8]
800162e: 2200 movs r2, #0
8001630: 605a str r2, [r3, #4]
WRITE_REG(dmarxdesc->DESC2, 0x0U);
8001632: 68bb ldr r3, [r7, #8]
8001634: 2200 movs r2, #0
8001636: 609a str r2, [r3, #8]
WRITE_REG(dmarxdesc->DESC3, 0x0U);
8001638: 68bb ldr r3, [r7, #8]
800163a: 2200 movs r2, #0
800163c: 60da str r2, [r3, #12]
WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
800163e: 68bb ldr r3, [r7, #8]
8001640: 2200 movs r2, #0
8001642: 621a str r2, [r3, #32]
WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
8001644: 68bb ldr r3, [r7, #8]
8001646: 2200 movs r2, #0
8001648: 625a str r2, [r3, #36] @ 0x24
/* Set Own bit of the Rx descriptor Status */
dmarxdesc->DESC0 = ETH_DMARXDESC_OWN;
800164a: 68bb ldr r3, [r7, #8]
800164c: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
8001650: 601a str r2, [r3, #0]
/* Set Buffer1 size and Second Address Chained bit */
dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH;
8001652: 687b ldr r3, [r7, #4]
8001654: 695b ldr r3, [r3, #20]
8001656: f443 4280 orr.w r2, r3, #16384 @ 0x4000
800165a: 68bb ldr r3, [r7, #8]
800165c: 605a str r2, [r3, #4]
/* Enable Ethernet DMA Rx Descriptor interrupt */
dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC;
800165e: 68bb ldr r3, [r7, #8]
8001660: 685b ldr r3, [r3, #4]
8001662: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001666: 68bb ldr r3, [r7, #8]
8001668: 605a str r2, [r3, #4]
/* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
800166a: 68b9 ldr r1, [r7, #8]
800166c: 687b ldr r3, [r7, #4]
800166e: 68fa ldr r2, [r7, #12]
8001670: 3212 adds r2, #18
8001672: f843 1022 str.w r1, [r3, r2, lsl #2]
if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U))
8001676: 68fb ldr r3, [r7, #12]
8001678: 2b02 cmp r3, #2
800167a: d80c bhi.n 8001696 <ETH_DMARxDescListInit+0x90>
{
WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U));
800167c: 687b ldr r3, [r7, #4]
800167e: 6919 ldr r1, [r3, #16]
8001680: 68fb ldr r3, [r7, #12]
8001682: 1c5a adds r2, r3, #1
8001684: 4613 mov r3, r2
8001686: 009b lsls r3, r3, #2
8001688: 4413 add r3, r2
800168a: 00db lsls r3, r3, #3
800168c: 440b add r3, r1
800168e: 461a mov r2, r3
8001690: 68bb ldr r3, [r7, #8]
8001692: 60da str r2, [r3, #12]
8001694: e004 b.n 80016a0 <ETH_DMARxDescListInit+0x9a>
}
else
{
WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc));
8001696: 687b ldr r3, [r7, #4]
8001698: 691b ldr r3, [r3, #16]
800169a: 461a mov r2, r3
800169c: 68bb ldr r3, [r7, #8]
800169e: 60da str r2, [r3, #12]
for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
80016a0: 68fb ldr r3, [r7, #12]
80016a2: 3301 adds r3, #1
80016a4: 60fb str r3, [r7, #12]
80016a6: 68fb ldr r3, [r7, #12]
80016a8: 2b03 cmp r3, #3
80016aa: d9b3 bls.n 8001614 <ETH_DMARxDescListInit+0xe>
}
}
WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
80016ac: 687b ldr r3, [r7, #4]
80016ae: 2200 movs r2, #0
80016b0: 65da str r2, [r3, #92] @ 0x5c
WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
80016b2: 687b ldr r3, [r7, #4]
80016b4: 2200 movs r2, #0
80016b6: 661a str r2, [r3, #96] @ 0x60
WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
80016b8: 687b ldr r3, [r7, #4]
80016ba: 2200 movs r2, #0
80016bc: 669a str r2, [r3, #104] @ 0x68
WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
80016be: 687b ldr r3, [r7, #4]
80016c0: 2200 movs r2, #0
80016c2: 66da str r2, [r3, #108] @ 0x6c
WRITE_REG(heth->RxDescList.ItMode, 0U);
80016c4: 687b ldr r3, [r7, #4]
80016c6: 2200 movs r2, #0
80016c8: 659a str r2, [r3, #88] @ 0x58
/* Set Receive Descriptor List Address */
WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc);
80016ca: 687b ldr r3, [r7, #4]
80016cc: 691a ldr r2, [r3, #16]
80016ce: 687b ldr r3, [r7, #4]
80016d0: 681b ldr r3, [r3, #0]
80016d2: f503 5380 add.w r3, r3, #4096 @ 0x1000
80016d6: 60da str r2, [r3, #12]
}
80016d8: bf00 nop
80016da: 3714 adds r7, #20
80016dc: 46bd mov sp, r7
80016de: f85d 7b04 ldr.w r7, [sp], #4
80016e2: 4770 bx lr
080016e4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80016e4: b480 push {r7}
80016e6: b089 sub sp, #36 @ 0x24
80016e8: af00 add r7, sp, #0
80016ea: 6078 str r0, [r7, #4]
80016ec: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80016ee: 2300 movs r3, #0
80016f0: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
80016f2: 2300 movs r3, #0
80016f4: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
80016f6: 2300 movs r3, #0
80016f8: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
80016fa: 2300 movs r3, #0
80016fc: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for (position = 0; position < GPIO_NUMBER; position++)
80016fe: 2300 movs r3, #0
8001700: 61fb str r3, [r7, #28]
8001702: e175 b.n 80019f0 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8001704: 2201 movs r2, #1
8001706: 69fb ldr r3, [r7, #28]
8001708: fa02 f303 lsl.w r3, r2, r3
800170c: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800170e: 683b ldr r3, [r7, #0]
8001710: 681b ldr r3, [r3, #0]
8001712: 697a ldr r2, [r7, #20]
8001714: 4013 ands r3, r2
8001716: 613b str r3, [r7, #16]
if (iocurrent == ioposition)
8001718: 693a ldr r2, [r7, #16]
800171a: 697b ldr r3, [r7, #20]
800171c: 429a cmp r2, r3
800171e: f040 8164 bne.w 80019ea <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001722: 683b ldr r3, [r7, #0]
8001724: 685b ldr r3, [r3, #4]
8001726: f003 0303 and.w r3, r3, #3
800172a: 2b01 cmp r3, #1
800172c: d005 beq.n 800173a <HAL_GPIO_Init+0x56>
800172e: 683b ldr r3, [r7, #0]
8001730: 685b ldr r3, [r3, #4]
8001732: f003 0303 and.w r3, r3, #3
8001736: 2b02 cmp r3, #2
8001738: d130 bne.n 800179c <HAL_GPIO_Init+0xb8>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800173a: 687b ldr r3, [r7, #4]
800173c: 689b ldr r3, [r3, #8]
800173e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8001740: 69fb ldr r3, [r7, #28]
8001742: 005b lsls r3, r3, #1
8001744: 2203 movs r2, #3
8001746: fa02 f303 lsl.w r3, r2, r3
800174a: 43db mvns r3, r3
800174c: 69ba ldr r2, [r7, #24]
800174e: 4013 ands r3, r2
8001750: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
8001752: 683b ldr r3, [r7, #0]
8001754: 68da ldr r2, [r3, #12]
8001756: 69fb ldr r3, [r7, #28]
8001758: 005b lsls r3, r3, #1
800175a: fa02 f303 lsl.w r3, r2, r3
800175e: 69ba ldr r2, [r7, #24]
8001760: 4313 orrs r3, r2
8001762: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001764: 687b ldr r3, [r7, #4]
8001766: 69ba ldr r2, [r7, #24]
8001768: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800176a: 687b ldr r3, [r7, #4]
800176c: 685b ldr r3, [r3, #4]
800176e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001770: 2201 movs r2, #1
8001772: 69fb ldr r3, [r7, #28]
8001774: fa02 f303 lsl.w r3, r2, r3
8001778: 43db mvns r3, r3
800177a: 69ba ldr r2, [r7, #24]
800177c: 4013 ands r3, r2
800177e: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001780: 683b ldr r3, [r7, #0]
8001782: 685b ldr r3, [r3, #4]
8001784: 091b lsrs r3, r3, #4
8001786: f003 0201 and.w r2, r3, #1
800178a: 69fb ldr r3, [r7, #28]
800178c: fa02 f303 lsl.w r3, r2, r3
8001790: 69ba ldr r2, [r7, #24]
8001792: 4313 orrs r3, r2
8001794: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001796: 687b ldr r3, [r7, #4]
8001798: 69ba ldr r2, [r7, #24]
800179a: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
800179c: 683b ldr r3, [r7, #0]
800179e: 685b ldr r3, [r3, #4]
80017a0: f003 0303 and.w r3, r3, #3
80017a4: 2b03 cmp r3, #3
80017a6: d017 beq.n 80017d8 <HAL_GPIO_Init+0xf4>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80017a8: 687b ldr r3, [r7, #4]
80017aa: 68db ldr r3, [r3, #12]
80017ac: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
80017ae: 69fb ldr r3, [r7, #28]
80017b0: 005b lsls r3, r3, #1
80017b2: 2203 movs r2, #3
80017b4: fa02 f303 lsl.w r3, r2, r3
80017b8: 43db mvns r3, r3
80017ba: 69ba ldr r2, [r7, #24]
80017bc: 4013 ands r3, r2
80017be: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
80017c0: 683b ldr r3, [r7, #0]
80017c2: 689a ldr r2, [r3, #8]
80017c4: 69fb ldr r3, [r7, #28]
80017c6: 005b lsls r3, r3, #1
80017c8: fa02 f303 lsl.w r3, r2, r3
80017cc: 69ba ldr r2, [r7, #24]
80017ce: 4313 orrs r3, r2
80017d0: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
80017d2: 687b ldr r3, [r7, #4]
80017d4: 69ba ldr r2, [r7, #24]
80017d6: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80017d8: 683b ldr r3, [r7, #0]
80017da: 685b ldr r3, [r3, #4]
80017dc: f003 0303 and.w r3, r3, #3
80017e0: 2b02 cmp r3, #2
80017e2: d123 bne.n 800182c <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
80017e4: 69fb ldr r3, [r7, #28]
80017e6: 08da lsrs r2, r3, #3
80017e8: 687b ldr r3, [r7, #4]
80017ea: 3208 adds r2, #8
80017ec: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80017f0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
80017f2: 69fb ldr r3, [r7, #28]
80017f4: f003 0307 and.w r3, r3, #7
80017f8: 009b lsls r3, r3, #2
80017fa: 220f movs r2, #15
80017fc: fa02 f303 lsl.w r3, r2, r3
8001800: 43db mvns r3, r3
8001802: 69ba ldr r2, [r7, #24]
8001804: 4013 ands r3, r2
8001806: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
8001808: 683b ldr r3, [r7, #0]
800180a: 691a ldr r2, [r3, #16]
800180c: 69fb ldr r3, [r7, #28]
800180e: f003 0307 and.w r3, r3, #7
8001812: 009b lsls r3, r3, #2
8001814: fa02 f303 lsl.w r3, r2, r3
8001818: 69ba ldr r2, [r7, #24]
800181a: 4313 orrs r3, r2
800181c: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
800181e: 69fb ldr r3, [r7, #28]
8001820: 08da lsrs r2, r3, #3
8001822: 687b ldr r3, [r7, #4]
8001824: 3208 adds r2, #8
8001826: 69b9 ldr r1, [r7, #24]
8001828: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800182c: 687b ldr r3, [r7, #4]
800182e: 681b ldr r3, [r3, #0]
8001830: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
8001832: 69fb ldr r3, [r7, #28]
8001834: 005b lsls r3, r3, #1
8001836: 2203 movs r2, #3
8001838: fa02 f303 lsl.w r3, r2, r3
800183c: 43db mvns r3, r3
800183e: 69ba ldr r2, [r7, #24]
8001840: 4013 ands r3, r2
8001842: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8001844: 683b ldr r3, [r7, #0]
8001846: 685b ldr r3, [r3, #4]
8001848: f003 0203 and.w r2, r3, #3
800184c: 69fb ldr r3, [r7, #28]
800184e: 005b lsls r3, r3, #1
8001850: fa02 f303 lsl.w r3, r2, r3
8001854: 69ba ldr r2, [r7, #24]
8001856: 4313 orrs r3, r2
8001858: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
800185a: 687b ldr r3, [r7, #4]
800185c: 69ba ldr r2, [r7, #24]
800185e: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001860: 683b ldr r3, [r7, #0]
8001862: 685b ldr r3, [r3, #4]
8001864: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001868: 2b00 cmp r3, #0
800186a: f000 80be beq.w 80019ea <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800186e: 4b66 ldr r3, [pc, #408] @ (8001a08 <HAL_GPIO_Init+0x324>)
8001870: 6c5b ldr r3, [r3, #68] @ 0x44
8001872: 4a65 ldr r2, [pc, #404] @ (8001a08 <HAL_GPIO_Init+0x324>)
8001874: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001878: 6453 str r3, [r2, #68] @ 0x44
800187a: 4b63 ldr r3, [pc, #396] @ (8001a08 <HAL_GPIO_Init+0x324>)
800187c: 6c5b ldr r3, [r3, #68] @ 0x44
800187e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001882: 60fb str r3, [r7, #12]
8001884: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
8001886: 4a61 ldr r2, [pc, #388] @ (8001a0c <HAL_GPIO_Init+0x328>)
8001888: 69fb ldr r3, [r7, #28]
800188a: 089b lsrs r3, r3, #2
800188c: 3302 adds r3, #2
800188e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001892: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8001894: 69fb ldr r3, [r7, #28]
8001896: f003 0303 and.w r3, r3, #3
800189a: 009b lsls r3, r3, #2
800189c: 220f movs r2, #15
800189e: fa02 f303 lsl.w r3, r2, r3
80018a2: 43db mvns r3, r3
80018a4: 69ba ldr r2, [r7, #24]
80018a6: 4013 ands r3, r2
80018a8: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
80018aa: 687b ldr r3, [r7, #4]
80018ac: 4a58 ldr r2, [pc, #352] @ (8001a10 <HAL_GPIO_Init+0x32c>)
80018ae: 4293 cmp r3, r2
80018b0: d037 beq.n 8001922 <HAL_GPIO_Init+0x23e>
80018b2: 687b ldr r3, [r7, #4]
80018b4: 4a57 ldr r2, [pc, #348] @ (8001a14 <HAL_GPIO_Init+0x330>)
80018b6: 4293 cmp r3, r2
80018b8: d031 beq.n 800191e <HAL_GPIO_Init+0x23a>
80018ba: 687b ldr r3, [r7, #4]
80018bc: 4a56 ldr r2, [pc, #344] @ (8001a18 <HAL_GPIO_Init+0x334>)
80018be: 4293 cmp r3, r2
80018c0: d02b beq.n 800191a <HAL_GPIO_Init+0x236>
80018c2: 687b ldr r3, [r7, #4]
80018c4: 4a55 ldr r2, [pc, #340] @ (8001a1c <HAL_GPIO_Init+0x338>)
80018c6: 4293 cmp r3, r2
80018c8: d025 beq.n 8001916 <HAL_GPIO_Init+0x232>
80018ca: 687b ldr r3, [r7, #4]
80018cc: 4a54 ldr r2, [pc, #336] @ (8001a20 <HAL_GPIO_Init+0x33c>)
80018ce: 4293 cmp r3, r2
80018d0: d01f beq.n 8001912 <HAL_GPIO_Init+0x22e>
80018d2: 687b ldr r3, [r7, #4]
80018d4: 4a53 ldr r2, [pc, #332] @ (8001a24 <HAL_GPIO_Init+0x340>)
80018d6: 4293 cmp r3, r2
80018d8: d019 beq.n 800190e <HAL_GPIO_Init+0x22a>
80018da: 687b ldr r3, [r7, #4]
80018dc: 4a52 ldr r2, [pc, #328] @ (8001a28 <HAL_GPIO_Init+0x344>)
80018de: 4293 cmp r3, r2
80018e0: d013 beq.n 800190a <HAL_GPIO_Init+0x226>
80018e2: 687b ldr r3, [r7, #4]
80018e4: 4a51 ldr r2, [pc, #324] @ (8001a2c <HAL_GPIO_Init+0x348>)
80018e6: 4293 cmp r3, r2
80018e8: d00d beq.n 8001906 <HAL_GPIO_Init+0x222>
80018ea: 687b ldr r3, [r7, #4]
80018ec: 4a50 ldr r2, [pc, #320] @ (8001a30 <HAL_GPIO_Init+0x34c>)
80018ee: 4293 cmp r3, r2
80018f0: d007 beq.n 8001902 <HAL_GPIO_Init+0x21e>
80018f2: 687b ldr r3, [r7, #4]
80018f4: 4a4f ldr r2, [pc, #316] @ (8001a34 <HAL_GPIO_Init+0x350>)
80018f6: 4293 cmp r3, r2
80018f8: d101 bne.n 80018fe <HAL_GPIO_Init+0x21a>
80018fa: 2309 movs r3, #9
80018fc: e012 b.n 8001924 <HAL_GPIO_Init+0x240>
80018fe: 230a movs r3, #10
8001900: e010 b.n 8001924 <HAL_GPIO_Init+0x240>
8001902: 2308 movs r3, #8
8001904: e00e b.n 8001924 <HAL_GPIO_Init+0x240>
8001906: 2307 movs r3, #7
8001908: e00c b.n 8001924 <HAL_GPIO_Init+0x240>
800190a: 2306 movs r3, #6
800190c: e00a b.n 8001924 <HAL_GPIO_Init+0x240>
800190e: 2305 movs r3, #5
8001910: e008 b.n 8001924 <HAL_GPIO_Init+0x240>
8001912: 2304 movs r3, #4
8001914: e006 b.n 8001924 <HAL_GPIO_Init+0x240>
8001916: 2303 movs r3, #3
8001918: e004 b.n 8001924 <HAL_GPIO_Init+0x240>
800191a: 2302 movs r3, #2
800191c: e002 b.n 8001924 <HAL_GPIO_Init+0x240>
800191e: 2301 movs r3, #1
8001920: e000 b.n 8001924 <HAL_GPIO_Init+0x240>
8001922: 2300 movs r3, #0
8001924: 69fa ldr r2, [r7, #28]
8001926: f002 0203 and.w r2, r2, #3
800192a: 0092 lsls r2, r2, #2
800192c: 4093 lsls r3, r2
800192e: 69ba ldr r2, [r7, #24]
8001930: 4313 orrs r3, r2
8001932: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
8001934: 4935 ldr r1, [pc, #212] @ (8001a0c <HAL_GPIO_Init+0x328>)
8001936: 69fb ldr r3, [r7, #28]
8001938: 089b lsrs r3, r3, #2
800193a: 3302 adds r3, #2
800193c: 69ba ldr r2, [r7, #24]
800193e: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001942: 4b3d ldr r3, [pc, #244] @ (8001a38 <HAL_GPIO_Init+0x354>)
8001944: 689b ldr r3, [r3, #8]
8001946: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001948: 693b ldr r3, [r7, #16]
800194a: 43db mvns r3, r3
800194c: 69ba ldr r2, [r7, #24]
800194e: 4013 ands r3, r2
8001950: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001952: 683b ldr r3, [r7, #0]
8001954: 685b ldr r3, [r3, #4]
8001956: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800195a: 2b00 cmp r3, #0
800195c: d003 beq.n 8001966 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
800195e: 69ba ldr r2, [r7, #24]
8001960: 693b ldr r3, [r7, #16]
8001962: 4313 orrs r3, r2
8001964: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001966: 4a34 ldr r2, [pc, #208] @ (8001a38 <HAL_GPIO_Init+0x354>)
8001968: 69bb ldr r3, [r7, #24]
800196a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800196c: 4b32 ldr r3, [pc, #200] @ (8001a38 <HAL_GPIO_Init+0x354>)
800196e: 68db ldr r3, [r3, #12]
8001970: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001972: 693b ldr r3, [r7, #16]
8001974: 43db mvns r3, r3
8001976: 69ba ldr r2, [r7, #24]
8001978: 4013 ands r3, r2
800197a: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
800197c: 683b ldr r3, [r7, #0]
800197e: 685b ldr r3, [r3, #4]
8001980: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001984: 2b00 cmp r3, #0
8001986: d003 beq.n 8001990 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8001988: 69ba ldr r2, [r7, #24]
800198a: 693b ldr r3, [r7, #16]
800198c: 4313 orrs r3, r2
800198e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001990: 4a29 ldr r2, [pc, #164] @ (8001a38 <HAL_GPIO_Init+0x354>)
8001992: 69bb ldr r3, [r7, #24]
8001994: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001996: 4b28 ldr r3, [pc, #160] @ (8001a38 <HAL_GPIO_Init+0x354>)
8001998: 685b ldr r3, [r3, #4]
800199a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800199c: 693b ldr r3, [r7, #16]
800199e: 43db mvns r3, r3
80019a0: 69ba ldr r2, [r7, #24]
80019a2: 4013 ands r3, r2
80019a4: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
80019a6: 683b ldr r3, [r7, #0]
80019a8: 685b ldr r3, [r3, #4]
80019aa: f403 3300 and.w r3, r3, #131072 @ 0x20000
80019ae: 2b00 cmp r3, #0
80019b0: d003 beq.n 80019ba <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
80019b2: 69ba ldr r2, [r7, #24]
80019b4: 693b ldr r3, [r7, #16]
80019b6: 4313 orrs r3, r2
80019b8: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80019ba: 4a1f ldr r2, [pc, #124] @ (8001a38 <HAL_GPIO_Init+0x354>)
80019bc: 69bb ldr r3, [r7, #24]
80019be: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80019c0: 4b1d ldr r3, [pc, #116] @ (8001a38 <HAL_GPIO_Init+0x354>)
80019c2: 681b ldr r3, [r3, #0]
80019c4: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80019c6: 693b ldr r3, [r7, #16]
80019c8: 43db mvns r3, r3
80019ca: 69ba ldr r2, [r7, #24]
80019cc: 4013 ands r3, r2
80019ce: 61bb str r3, [r7, #24]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80019d0: 683b ldr r3, [r7, #0]
80019d2: 685b ldr r3, [r3, #4]
80019d4: f403 3380 and.w r3, r3, #65536 @ 0x10000
80019d8: 2b00 cmp r3, #0
80019da: d003 beq.n 80019e4 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
80019dc: 69ba ldr r2, [r7, #24]
80019de: 693b ldr r3, [r7, #16]
80019e0: 4313 orrs r3, r2
80019e2: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80019e4: 4a14 ldr r2, [pc, #80] @ (8001a38 <HAL_GPIO_Init+0x354>)
80019e6: 69bb ldr r3, [r7, #24]
80019e8: 6013 str r3, [r2, #0]
for (position = 0; position < GPIO_NUMBER; position++)
80019ea: 69fb ldr r3, [r7, #28]
80019ec: 3301 adds r3, #1
80019ee: 61fb str r3, [r7, #28]
80019f0: 69fb ldr r3, [r7, #28]
80019f2: 2b0f cmp r3, #15
80019f4: f67f ae86 bls.w 8001704 <HAL_GPIO_Init+0x20>
}
}
}
}
80019f8: bf00 nop
80019fa: bf00 nop
80019fc: 3724 adds r7, #36 @ 0x24
80019fe: 46bd mov sp, r7
8001a00: f85d 7b04 ldr.w r7, [sp], #4
8001a04: 4770 bx lr
8001a06: bf00 nop
8001a08: 40023800 .word 0x40023800
8001a0c: 40013800 .word 0x40013800
8001a10: 40020000 .word 0x40020000
8001a14: 40020400 .word 0x40020400
8001a18: 40020800 .word 0x40020800
8001a1c: 40020c00 .word 0x40020c00
8001a20: 40021000 .word 0x40021000
8001a24: 40021400 .word 0x40021400
8001a28: 40021800 .word 0x40021800
8001a2c: 40021c00 .word 0x40021c00
8001a30: 40022000 .word 0x40022000
8001a34: 40022400 .word 0x40022400
8001a38: 40013c00 .word 0x40013c00
08001a3c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001a3c: b480 push {r7}
8001a3e: b083 sub sp, #12
8001a40: af00 add r7, sp, #0
8001a42: 6078 str r0, [r7, #4]
8001a44: 460b mov r3, r1
8001a46: 807b strh r3, [r7, #2]
8001a48: 4613 mov r3, r2
8001a4a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001a4c: 787b ldrb r3, [r7, #1]
8001a4e: 2b00 cmp r3, #0
8001a50: d003 beq.n 8001a5a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001a52: 887a ldrh r2, [r7, #2]
8001a54: 687b ldr r3, [r7, #4]
8001a56: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8001a58: e003 b.n 8001a62 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
8001a5a: 887b ldrh r3, [r7, #2]
8001a5c: 041a lsls r2, r3, #16
8001a5e: 687b ldr r3, [r7, #4]
8001a60: 619a str r2, [r3, #24]
}
8001a62: bf00 nop
8001a64: 370c adds r7, #12
8001a66: 46bd mov sp, r7
8001a68: f85d 7b04 ldr.w r7, [sp], #4
8001a6c: 4770 bx lr
08001a6e <HAL_GPIO_TogglePin>:
* @param GPIO_Pin Specifies the pins to be toggled.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
8001a6e: b480 push {r7}
8001a70: b085 sub sp, #20
8001a72: af00 add r7, sp, #0
8001a74: 6078 str r0, [r7, #4]
8001a76: 460b mov r3, r1
8001a78: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: 695b ldr r3, [r3, #20]
8001a7e: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8001a80: 887a ldrh r2, [r7, #2]
8001a82: 68fb ldr r3, [r7, #12]
8001a84: 4013 ands r3, r2
8001a86: 041a lsls r2, r3, #16
8001a88: 68fb ldr r3, [r7, #12]
8001a8a: 43d9 mvns r1, r3
8001a8c: 887b ldrh r3, [r7, #2]
8001a8e: 400b ands r3, r1
8001a90: 431a orrs r2, r3
8001a92: 687b ldr r3, [r7, #4]
8001a94: 619a str r2, [r3, #24]
}
8001a96: bf00 nop
8001a98: 3714 adds r7, #20
8001a9a: 46bd mov sp, r7
8001a9c: f85d 7b04 ldr.w r7, [sp], #4
8001aa0: 4770 bx lr
08001aa2 <HAL_PCD_Init>:
* parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
8001aa2: b580 push {r7, lr}
8001aa4: b086 sub sp, #24
8001aa6: af02 add r7, sp, #8
8001aa8: 6078 str r0, [r7, #4]
const USB_OTG_GlobalTypeDef *USBx;
#endif /* defined (USB_OTG_FS) */
uint8_t i;
/* Check the PCD handle allocation */
if (hpcd == NULL)
8001aaa: 687b ldr r3, [r7, #4]
8001aac: 2b00 cmp r3, #0
8001aae: d101 bne.n 8001ab4 <HAL_PCD_Init+0x12>
{
return HAL_ERROR;
8001ab0: 2301 movs r3, #1
8001ab2: e108 b.n 8001cc6 <HAL_PCD_Init+0x224>
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
#if defined (USB_OTG_FS)
USBx = hpcd->Instance;
8001ab4: 687b ldr r3, [r7, #4]
8001ab6: 681b ldr r3, [r3, #0]
8001ab8: 60bb str r3, [r7, #8]
#endif /* defined (USB_OTG_FS) */
if (hpcd->State == HAL_PCD_STATE_RESET)
8001aba: 687b ldr r3, [r7, #4]
8001abc: f893 3495 ldrb.w r3, [r3, #1173] @ 0x495
8001ac0: b2db uxtb r3, r3
8001ac2: 2b00 cmp r3, #0
8001ac4: d106 bne.n 8001ad4 <HAL_PCD_Init+0x32>
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
8001ac6: 687b ldr r3, [r7, #4]
8001ac8: 2200 movs r2, #0
8001aca: f883 2494 strb.w r2, [r3, #1172] @ 0x494
/* Init the low level hardware */
hpcd->MspInitCallback(hpcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
8001ace: 6878 ldr r0, [r7, #4]
8001ad0: f7ff f86e bl 8000bb0 <HAL_PCD_MspInit>
#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
8001ad4: 687b ldr r3, [r7, #4]
8001ad6: 2203 movs r2, #3
8001ad8: f883 2495 strb.w r2, [r3, #1173] @ 0x495
#if defined (USB_OTG_FS)
/* Disable DMA mode for FS instance */
if (USBx == USB_OTG_FS)
8001adc: 68bb ldr r3, [r7, #8]
8001ade: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8001ae2: d102 bne.n 8001aea <HAL_PCD_Init+0x48>
{
hpcd->Init.dma_enable = 0U;
8001ae4: 687b ldr r3, [r7, #4]
8001ae6: 2200 movs r2, #0
8001ae8: 719a strb r2, [r3, #6]
}
#endif /* defined (USB_OTG_FS) */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
8001aea: 687b ldr r3, [r7, #4]
8001aec: 681b ldr r3, [r3, #0]
8001aee: 4618 mov r0, r3
8001af0: f001 ff96 bl 8003a20 <USB_DisableGlobalInt>
/*Init the Core (common init.) */
if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8001af4: 687b ldr r3, [r7, #4]
8001af6: 6818 ldr r0, [r3, #0]
8001af8: 687b ldr r3, [r7, #4]
8001afa: 7c1a ldrb r2, [r3, #16]
8001afc: f88d 2000 strb.w r2, [sp]
8001b00: 3304 adds r3, #4
8001b02: cb0e ldmia r3, {r1, r2, r3}
8001b04: f001 ff32 bl 800396c <USB_CoreInit>
8001b08: 4603 mov r3, r0
8001b0a: 2b00 cmp r3, #0
8001b0c: d005 beq.n 8001b1a <HAL_PCD_Init+0x78>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 2202 movs r2, #2
8001b12: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8001b16: 2301 movs r3, #1
8001b18: e0d5 b.n 8001cc6 <HAL_PCD_Init+0x224>
}
/* Force Device Mode */
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
8001b1a: 687b ldr r3, [r7, #4]
8001b1c: 681b ldr r3, [r3, #0]
8001b1e: 2100 movs r1, #0
8001b20: 4618 mov r0, r3
8001b22: f001 ff8e bl 8003a42 <USB_SetCurrentMode>
8001b26: 4603 mov r3, r0
8001b28: 2b00 cmp r3, #0
8001b2a: d005 beq.n 8001b38 <HAL_PCD_Init+0x96>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001b2c: 687b ldr r3, [r7, #4]
8001b2e: 2202 movs r2, #2
8001b30: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8001b34: 2301 movs r3, #1
8001b36: e0c6 b.n 8001cc6 <HAL_PCD_Init+0x224>
}
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001b38: 2300 movs r3, #0
8001b3a: 73fb strb r3, [r7, #15]
8001b3c: e04a b.n 8001bd4 <HAL_PCD_Init+0x132>
{
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
8001b3e: 7bfa ldrb r2, [r7, #15]
8001b40: 6879 ldr r1, [r7, #4]
8001b42: 4613 mov r3, r2
8001b44: 00db lsls r3, r3, #3
8001b46: 4413 add r3, r2
8001b48: 009b lsls r3, r3, #2
8001b4a: 440b add r3, r1
8001b4c: 3315 adds r3, #21
8001b4e: 2201 movs r2, #1
8001b50: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].num = i;
8001b52: 7bfa ldrb r2, [r7, #15]
8001b54: 6879 ldr r1, [r7, #4]
8001b56: 4613 mov r3, r2
8001b58: 00db lsls r3, r3, #3
8001b5a: 4413 add r3, r2
8001b5c: 009b lsls r3, r3, #2
8001b5e: 440b add r3, r1
8001b60: 3314 adds r3, #20
8001b62: 7bfa ldrb r2, [r7, #15]
8001b64: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].tx_fifo_num = i;
8001b66: 7bfa ldrb r2, [r7, #15]
8001b68: 7bfb ldrb r3, [r7, #15]
8001b6a: b298 uxth r0, r3
8001b6c: 6879 ldr r1, [r7, #4]
8001b6e: 4613 mov r3, r2
8001b70: 00db lsls r3, r3, #3
8001b72: 4413 add r3, r2
8001b74: 009b lsls r3, r3, #2
8001b76: 440b add r3, r1
8001b78: 332e adds r3, #46 @ 0x2e
8001b7a: 4602 mov r2, r0
8001b7c: 801a strh r2, [r3, #0]
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
8001b7e: 7bfa ldrb r2, [r7, #15]
8001b80: 6879 ldr r1, [r7, #4]
8001b82: 4613 mov r3, r2
8001b84: 00db lsls r3, r3, #3
8001b86: 4413 add r3, r2
8001b88: 009b lsls r3, r3, #2
8001b8a: 440b add r3, r1
8001b8c: 3318 adds r3, #24
8001b8e: 2200 movs r2, #0
8001b90: 701a strb r2, [r3, #0]
hpcd->IN_ep[i].maxpacket = 0U;
8001b92: 7bfa ldrb r2, [r7, #15]
8001b94: 6879 ldr r1, [r7, #4]
8001b96: 4613 mov r3, r2
8001b98: 00db lsls r3, r3, #3
8001b9a: 4413 add r3, r2
8001b9c: 009b lsls r3, r3, #2
8001b9e: 440b add r3, r1
8001ba0: 331c adds r3, #28
8001ba2: 2200 movs r2, #0
8001ba4: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_buff = 0U;
8001ba6: 7bfa ldrb r2, [r7, #15]
8001ba8: 6879 ldr r1, [r7, #4]
8001baa: 4613 mov r3, r2
8001bac: 00db lsls r3, r3, #3
8001bae: 4413 add r3, r2
8001bb0: 009b lsls r3, r3, #2
8001bb2: 440b add r3, r1
8001bb4: 3320 adds r3, #32
8001bb6: 2200 movs r2, #0
8001bb8: 601a str r2, [r3, #0]
hpcd->IN_ep[i].xfer_len = 0U;
8001bba: 7bfa ldrb r2, [r7, #15]
8001bbc: 6879 ldr r1, [r7, #4]
8001bbe: 4613 mov r3, r2
8001bc0: 00db lsls r3, r3, #3
8001bc2: 4413 add r3, r2
8001bc4: 009b lsls r3, r3, #2
8001bc6: 440b add r3, r1
8001bc8: 3324 adds r3, #36 @ 0x24
8001bca: 2200 movs r2, #0
8001bcc: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001bce: 7bfb ldrb r3, [r7, #15]
8001bd0: 3301 adds r3, #1
8001bd2: 73fb strb r3, [r7, #15]
8001bd4: 687b ldr r3, [r7, #4]
8001bd6: 791b ldrb r3, [r3, #4]
8001bd8: 7bfa ldrb r2, [r7, #15]
8001bda: 429a cmp r2, r3
8001bdc: d3af bcc.n 8001b3e <HAL_PCD_Init+0x9c>
}
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001bde: 2300 movs r3, #0
8001be0: 73fb strb r3, [r7, #15]
8001be2: e044 b.n 8001c6e <HAL_PCD_Init+0x1cc>
{
hpcd->OUT_ep[i].is_in = 0U;
8001be4: 7bfa ldrb r2, [r7, #15]
8001be6: 6879 ldr r1, [r7, #4]
8001be8: 4613 mov r3, r2
8001bea: 00db lsls r3, r3, #3
8001bec: 4413 add r3, r2
8001bee: 009b lsls r3, r3, #2
8001bf0: 440b add r3, r1
8001bf2: f203 2355 addw r3, r3, #597 @ 0x255
8001bf6: 2200 movs r2, #0
8001bf8: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].num = i;
8001bfa: 7bfa ldrb r2, [r7, #15]
8001bfc: 6879 ldr r1, [r7, #4]
8001bfe: 4613 mov r3, r2
8001c00: 00db lsls r3, r3, #3
8001c02: 4413 add r3, r2
8001c04: 009b lsls r3, r3, #2
8001c06: 440b add r3, r1
8001c08: f503 7315 add.w r3, r3, #596 @ 0x254
8001c0c: 7bfa ldrb r2, [r7, #15]
8001c0e: 701a strb r2, [r3, #0]
/* Control until ep is activated */
hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
8001c10: 7bfa ldrb r2, [r7, #15]
8001c12: 6879 ldr r1, [r7, #4]
8001c14: 4613 mov r3, r2
8001c16: 00db lsls r3, r3, #3
8001c18: 4413 add r3, r2
8001c1a: 009b lsls r3, r3, #2
8001c1c: 440b add r3, r1
8001c1e: f503 7316 add.w r3, r3, #600 @ 0x258
8001c22: 2200 movs r2, #0
8001c24: 701a strb r2, [r3, #0]
hpcd->OUT_ep[i].maxpacket = 0U;
8001c26: 7bfa ldrb r2, [r7, #15]
8001c28: 6879 ldr r1, [r7, #4]
8001c2a: 4613 mov r3, r2
8001c2c: 00db lsls r3, r3, #3
8001c2e: 4413 add r3, r2
8001c30: 009b lsls r3, r3, #2
8001c32: 440b add r3, r1
8001c34: f503 7317 add.w r3, r3, #604 @ 0x25c
8001c38: 2200 movs r2, #0
8001c3a: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_buff = 0U;
8001c3c: 7bfa ldrb r2, [r7, #15]
8001c3e: 6879 ldr r1, [r7, #4]
8001c40: 4613 mov r3, r2
8001c42: 00db lsls r3, r3, #3
8001c44: 4413 add r3, r2
8001c46: 009b lsls r3, r3, #2
8001c48: 440b add r3, r1
8001c4a: f503 7318 add.w r3, r3, #608 @ 0x260
8001c4e: 2200 movs r2, #0
8001c50: 601a str r2, [r3, #0]
hpcd->OUT_ep[i].xfer_len = 0U;
8001c52: 7bfa ldrb r2, [r7, #15]
8001c54: 6879 ldr r1, [r7, #4]
8001c56: 4613 mov r3, r2
8001c58: 00db lsls r3, r3, #3
8001c5a: 4413 add r3, r2
8001c5c: 009b lsls r3, r3, #2
8001c5e: 440b add r3, r1
8001c60: f503 7319 add.w r3, r3, #612 @ 0x264
8001c64: 2200 movs r2, #0
8001c66: 601a str r2, [r3, #0]
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
8001c68: 7bfb ldrb r3, [r7, #15]
8001c6a: 3301 adds r3, #1
8001c6c: 73fb strb r3, [r7, #15]
8001c6e: 687b ldr r3, [r7, #4]
8001c70: 791b ldrb r3, [r3, #4]
8001c72: 7bfa ldrb r2, [r7, #15]
8001c74: 429a cmp r2, r3
8001c76: d3b5 bcc.n 8001be4 <HAL_PCD_Init+0x142>
}
/* Init Device */
if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 6818 ldr r0, [r3, #0]
8001c7c: 687b ldr r3, [r7, #4]
8001c7e: 7c1a ldrb r2, [r3, #16]
8001c80: f88d 2000 strb.w r2, [sp]
8001c84: 3304 adds r3, #4
8001c86: cb0e ldmia r3, {r1, r2, r3}
8001c88: f001 ff28 bl 8003adc <USB_DevInit>
8001c8c: 4603 mov r3, r0
8001c8e: 2b00 cmp r3, #0
8001c90: d005 beq.n 8001c9e <HAL_PCD_Init+0x1fc>
{
hpcd->State = HAL_PCD_STATE_ERROR;
8001c92: 687b ldr r3, [r7, #4]
8001c94: 2202 movs r2, #2
8001c96: f883 2495 strb.w r2, [r3, #1173] @ 0x495
return HAL_ERROR;
8001c9a: 2301 movs r3, #1
8001c9c: e013 b.n 8001cc6 <HAL_PCD_Init+0x224>
}
hpcd->USB_Address = 0U;
8001c9e: 687b ldr r3, [r7, #4]
8001ca0: 2200 movs r2, #0
8001ca2: 745a strb r2, [r3, #17]
hpcd->State = HAL_PCD_STATE_READY;
8001ca4: 687b ldr r3, [r7, #4]
8001ca6: 2201 movs r2, #1
8001ca8: f883 2495 strb.w r2, [r3, #1173] @ 0x495
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
8001cac: 687b ldr r3, [r7, #4]
8001cae: 7b1b ldrb r3, [r3, #12]
8001cb0: 2b01 cmp r3, #1
8001cb2: d102 bne.n 8001cba <HAL_PCD_Init+0x218>
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
8001cb4: 6878 ldr r0, [r7, #4]
8001cb6: f000 f80b bl 8001cd0 <HAL_PCDEx_ActivateLPM>
}
(void)USB_DevDisconnect(hpcd->Instance);
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 681b ldr r3, [r3, #0]
8001cbe: 4618 mov r0, r3
8001cc0: f002 f8e3 bl 8003e8a <USB_DevDisconnect>
return HAL_OK;
8001cc4: 2300 movs r3, #0
}
8001cc6: 4618 mov r0, r3
8001cc8: 3710 adds r7, #16
8001cca: 46bd mov sp, r7
8001ccc: bd80 pop {r7, pc}
...
08001cd0 <HAL_PCDEx_ActivateLPM>:
* @brief Activate LPM feature.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
8001cd0: b480 push {r7}
8001cd2: b085 sub sp, #20
8001cd4: af00 add r7, sp, #0
8001cd6: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
8001cd8: 687b ldr r3, [r7, #4]
8001cda: 681b ldr r3, [r3, #0]
8001cdc: 60fb str r3, [r7, #12]
hpcd->lpm_active = 1U;
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 2201 movs r2, #1
8001ce2: f8c3 24d8 str.w r2, [r3, #1240] @ 0x4d8
hpcd->LPM_State = LPM_L0;
8001ce6: 687b ldr r3, [r7, #4]
8001ce8: 2200 movs r2, #0
8001cea: f883 24cc strb.w r2, [r3, #1228] @ 0x4cc
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
8001cee: 68fb ldr r3, [r7, #12]
8001cf0: 699b ldr r3, [r3, #24]
8001cf2: f043 6200 orr.w r2, r3, #134217728 @ 0x8000000
8001cf6: 68fb ldr r3, [r7, #12]
8001cf8: 619a str r2, [r3, #24]
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
8001cfa: 68fb ldr r3, [r7, #12]
8001cfc: 6d5a ldr r2, [r3, #84] @ 0x54
8001cfe: 4b05 ldr r3, [pc, #20] @ (8001d14 <HAL_PCDEx_ActivateLPM+0x44>)
8001d00: 4313 orrs r3, r2
8001d02: 68fa ldr r2, [r7, #12]
8001d04: 6553 str r3, [r2, #84] @ 0x54
return HAL_OK;
8001d06: 2300 movs r3, #0
}
8001d08: 4618 mov r0, r3
8001d0a: 3714 adds r7, #20
8001d0c: 46bd mov sp, r7
8001d0e: f85d 7b04 ldr.w r7, [sp], #4
8001d12: 4770 bx lr
8001d14: 10000003 .word 0x10000003
08001d18 <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
8001d18: b480 push {r7}
8001d1a: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8001d1c: 4b05 ldr r3, [pc, #20] @ (8001d34 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001d1e: 681b ldr r3, [r3, #0]
8001d20: 4a04 ldr r2, [pc, #16] @ (8001d34 <HAL_PWR_EnableBkUpAccess+0x1c>)
8001d22: f443 7380 orr.w r3, r3, #256 @ 0x100
8001d26: 6013 str r3, [r2, #0]
}
8001d28: bf00 nop
8001d2a: 46bd mov sp, r7
8001d2c: f85d 7b04 ldr.w r7, [sp], #4
8001d30: 4770 bx lr
8001d32: bf00 nop
8001d34: 40007000 .word 0x40007000
08001d38 <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
8001d38: b580 push {r7, lr}
8001d3a: b082 sub sp, #8
8001d3c: af00 add r7, sp, #0
uint32_t tickstart = 0;
8001d3e: 2300 movs r3, #0
8001d40: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001d42: 4b23 ldr r3, [pc, #140] @ (8001dd0 <HAL_PWREx_EnableOverDrive+0x98>)
8001d44: 6c1b ldr r3, [r3, #64] @ 0x40
8001d46: 4a22 ldr r2, [pc, #136] @ (8001dd0 <HAL_PWREx_EnableOverDrive+0x98>)
8001d48: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001d4c: 6413 str r3, [r2, #64] @ 0x40
8001d4e: 4b20 ldr r3, [pc, #128] @ (8001dd0 <HAL_PWREx_EnableOverDrive+0x98>)
8001d50: 6c1b ldr r3, [r3, #64] @ 0x40
8001d52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001d56: 603b str r3, [r7, #0]
8001d58: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
8001d5a: 4b1e ldr r3, [pc, #120] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001d5c: 681b ldr r3, [r3, #0]
8001d5e: 4a1d ldr r2, [pc, #116] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001d60: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001d64: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001d66: f7ff f859 bl 8000e1c <HAL_GetTick>
8001d6a: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001d6c: e009 b.n 8001d82 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001d6e: f7ff f855 bl 8000e1c <HAL_GetTick>
8001d72: 4602 mov r2, r0
8001d74: 687b ldr r3, [r7, #4]
8001d76: 1ad3 subs r3, r2, r3
8001d78: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001d7c: d901 bls.n 8001d82 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8001d7e: 2303 movs r3, #3
8001d80: e022 b.n 8001dc8 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8001d82: 4b14 ldr r3, [pc, #80] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001d84: 685b ldr r3, [r3, #4]
8001d86: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001d8a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001d8e: d1ee bne.n 8001d6e <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8001d90: 4b10 ldr r3, [pc, #64] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001d92: 681b ldr r3, [r3, #0]
8001d94: 4a0f ldr r2, [pc, #60] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001d96: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8001d9a: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001d9c: f7ff f83e bl 8000e1c <HAL_GetTick>
8001da0: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001da2: e009 b.n 8001db8 <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8001da4: f7ff f83a bl 8000e1c <HAL_GetTick>
8001da8: 4602 mov r2, r0
8001daa: 687b ldr r3, [r7, #4]
8001dac: 1ad3 subs r3, r2, r3
8001dae: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8001db2: d901 bls.n 8001db8 <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8001db4: 2303 movs r3, #3
8001db6: e007 b.n 8001dc8 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8001db8: 4b06 ldr r3, [pc, #24] @ (8001dd4 <HAL_PWREx_EnableOverDrive+0x9c>)
8001dba: 685b ldr r3, [r3, #4]
8001dbc: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001dc0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8001dc4: d1ee bne.n 8001da4 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8001dc6: 2300 movs r3, #0
}
8001dc8: 4618 mov r0, r3
8001dca: 3708 adds r7, #8
8001dcc: 46bd mov sp, r7
8001dce: bd80 pop {r7, pc}
8001dd0: 40023800 .word 0x40023800
8001dd4: 40007000 .word 0x40007000
08001dd8 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001dd8: b580 push {r7, lr}
8001dda: b086 sub sp, #24
8001ddc: af00 add r7, sp, #0
8001dde: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
8001de0: 2300 movs r3, #0
8001de2: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8001de4: 687b ldr r3, [r7, #4]
8001de6: 2b00 cmp r3, #0
8001de8: d101 bne.n 8001dee <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
8001dea: 2301 movs r3, #1
8001dec: e29b b.n 8002326 <HAL_RCC_OscConfig+0x54e>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001dee: 687b ldr r3, [r7, #4]
8001df0: 681b ldr r3, [r3, #0]
8001df2: f003 0301 and.w r3, r3, #1
8001df6: 2b00 cmp r3, #0
8001df8: f000 8087 beq.w 8001f0a <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001dfc: 4b96 ldr r3, [pc, #600] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001dfe: 689b ldr r3, [r3, #8]
8001e00: f003 030c and.w r3, r3, #12
8001e04: 2b04 cmp r3, #4
8001e06: d00c beq.n 8001e22 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8001e08: 4b93 ldr r3, [pc, #588] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e0a: 689b ldr r3, [r3, #8]
8001e0c: f003 030c and.w r3, r3, #12
8001e10: 2b08 cmp r3, #8
8001e12: d112 bne.n 8001e3a <HAL_RCC_OscConfig+0x62>
8001e14: 4b90 ldr r3, [pc, #576] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e16: 685b ldr r3, [r3, #4]
8001e18: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001e1c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8001e20: d10b bne.n 8001e3a <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001e22: 4b8d ldr r3, [pc, #564] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e24: 681b ldr r3, [r3, #0]
8001e26: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001e2a: 2b00 cmp r3, #0
8001e2c: d06c beq.n 8001f08 <HAL_RCC_OscConfig+0x130>
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 685b ldr r3, [r3, #4]
8001e32: 2b00 cmp r3, #0
8001e34: d168 bne.n 8001f08 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
8001e36: 2301 movs r3, #1
8001e38: e275 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001e3a: 687b ldr r3, [r7, #4]
8001e3c: 685b ldr r3, [r3, #4]
8001e3e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8001e42: d106 bne.n 8001e52 <HAL_RCC_OscConfig+0x7a>
8001e44: 4b84 ldr r3, [pc, #528] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e46: 681b ldr r3, [r3, #0]
8001e48: 4a83 ldr r2, [pc, #524] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e4a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001e4e: 6013 str r3, [r2, #0]
8001e50: e02e b.n 8001eb0 <HAL_RCC_OscConfig+0xd8>
8001e52: 687b ldr r3, [r7, #4]
8001e54: 685b ldr r3, [r3, #4]
8001e56: 2b00 cmp r3, #0
8001e58: d10c bne.n 8001e74 <HAL_RCC_OscConfig+0x9c>
8001e5a: 4b7f ldr r3, [pc, #508] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e5c: 681b ldr r3, [r3, #0]
8001e5e: 4a7e ldr r2, [pc, #504] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e60: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001e64: 6013 str r3, [r2, #0]
8001e66: 4b7c ldr r3, [pc, #496] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e68: 681b ldr r3, [r3, #0]
8001e6a: 4a7b ldr r2, [pc, #492] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e6c: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001e70: 6013 str r3, [r2, #0]
8001e72: e01d b.n 8001eb0 <HAL_RCC_OscConfig+0xd8>
8001e74: 687b ldr r3, [r7, #4]
8001e76: 685b ldr r3, [r3, #4]
8001e78: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8001e7c: d10c bne.n 8001e98 <HAL_RCC_OscConfig+0xc0>
8001e7e: 4b76 ldr r3, [pc, #472] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e80: 681b ldr r3, [r3, #0]
8001e82: 4a75 ldr r2, [pc, #468] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e84: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8001e88: 6013 str r3, [r2, #0]
8001e8a: 4b73 ldr r3, [pc, #460] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e8c: 681b ldr r3, [r3, #0]
8001e8e: 4a72 ldr r2, [pc, #456] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e90: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001e94: 6013 str r3, [r2, #0]
8001e96: e00b b.n 8001eb0 <HAL_RCC_OscConfig+0xd8>
8001e98: 4b6f ldr r3, [pc, #444] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: 4a6e ldr r2, [pc, #440] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001e9e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8001ea2: 6013 str r3, [r2, #0]
8001ea4: 4b6c ldr r3, [pc, #432] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001ea6: 681b ldr r3, [r3, #0]
8001ea8: 4a6b ldr r2, [pc, #428] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001eaa: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8001eae: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001eb0: 687b ldr r3, [r7, #4]
8001eb2: 685b ldr r3, [r3, #4]
8001eb4: 2b00 cmp r3, #0
8001eb6: d013 beq.n 8001ee0 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001eb8: f7fe ffb0 bl 8000e1c <HAL_GetTick>
8001ebc: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001ebe: e008 b.n 8001ed2 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001ec0: f7fe ffac bl 8000e1c <HAL_GetTick>
8001ec4: 4602 mov r2, r0
8001ec6: 693b ldr r3, [r7, #16]
8001ec8: 1ad3 subs r3, r2, r3
8001eca: 2b64 cmp r3, #100 @ 0x64
8001ecc: d901 bls.n 8001ed2 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001ece: 2303 movs r3, #3
8001ed0: e229 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001ed2: 4b61 ldr r3, [pc, #388] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001ed4: 681b ldr r3, [r3, #0]
8001ed6: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001eda: 2b00 cmp r3, #0
8001edc: d0f0 beq.n 8001ec0 <HAL_RCC_OscConfig+0xe8>
8001ede: e014 b.n 8001f0a <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ee0: f7fe ff9c bl 8000e1c <HAL_GetTick>
8001ee4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001ee6: e008 b.n 8001efa <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8001ee8: f7fe ff98 bl 8000e1c <HAL_GetTick>
8001eec: 4602 mov r2, r0
8001eee: 693b ldr r3, [r7, #16]
8001ef0: 1ad3 subs r3, r2, r3
8001ef2: 2b64 cmp r3, #100 @ 0x64
8001ef4: d901 bls.n 8001efa <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
8001ef6: 2303 movs r3, #3
8001ef8: e215 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001efa: 4b57 ldr r3, [pc, #348] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001efc: 681b ldr r3, [r3, #0]
8001efe: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001f02: 2b00 cmp r3, #0
8001f04: d1f0 bne.n 8001ee8 <HAL_RCC_OscConfig+0x110>
8001f06: e000 b.n 8001f0a <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001f08: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001f0a: 687b ldr r3, [r7, #4]
8001f0c: 681b ldr r3, [r3, #0]
8001f0e: f003 0302 and.w r3, r3, #2
8001f12: 2b00 cmp r3, #0
8001f14: d069 beq.n 8001fea <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001f16: 4b50 ldr r3, [pc, #320] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f18: 689b ldr r3, [r3, #8]
8001f1a: f003 030c and.w r3, r3, #12
8001f1e: 2b00 cmp r3, #0
8001f20: d00b beq.n 8001f3a <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001f22: 4b4d ldr r3, [pc, #308] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f24: 689b ldr r3, [r3, #8]
8001f26: f003 030c and.w r3, r3, #12
8001f2a: 2b08 cmp r3, #8
8001f2c: d11c bne.n 8001f68 <HAL_RCC_OscConfig+0x190>
8001f2e: 4b4a ldr r3, [pc, #296] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f30: 685b ldr r3, [r3, #4]
8001f32: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8001f36: 2b00 cmp r3, #0
8001f38: d116 bne.n 8001f68 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001f3a: 4b47 ldr r3, [pc, #284] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f3c: 681b ldr r3, [r3, #0]
8001f3e: f003 0302 and.w r3, r3, #2
8001f42: 2b00 cmp r3, #0
8001f44: d005 beq.n 8001f52 <HAL_RCC_OscConfig+0x17a>
8001f46: 687b ldr r3, [r7, #4]
8001f48: 68db ldr r3, [r3, #12]
8001f4a: 2b01 cmp r3, #1
8001f4c: d001 beq.n 8001f52 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8001f4e: 2301 movs r3, #1
8001f50: e1e9 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001f52: 4b41 ldr r3, [pc, #260] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f54: 681b ldr r3, [r3, #0]
8001f56: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 691b ldr r3, [r3, #16]
8001f5e: 00db lsls r3, r3, #3
8001f60: 493d ldr r1, [pc, #244] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f62: 4313 orrs r3, r2
8001f64: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001f66: e040 b.n 8001fea <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8001f68: 687b ldr r3, [r7, #4]
8001f6a: 68db ldr r3, [r3, #12]
8001f6c: 2b00 cmp r3, #0
8001f6e: d023 beq.n 8001fb8 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001f70: 4b39 ldr r3, [pc, #228] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f72: 681b ldr r3, [r3, #0]
8001f74: 4a38 ldr r2, [pc, #224] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f76: f043 0301 orr.w r3, r3, #1
8001f7a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001f7c: f7fe ff4e bl 8000e1c <HAL_GetTick>
8001f80: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001f82: e008 b.n 8001f96 <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001f84: f7fe ff4a bl 8000e1c <HAL_GetTick>
8001f88: 4602 mov r2, r0
8001f8a: 693b ldr r3, [r7, #16]
8001f8c: 1ad3 subs r3, r2, r3
8001f8e: 2b02 cmp r3, #2
8001f90: d901 bls.n 8001f96 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8001f92: 2303 movs r3, #3
8001f94: e1c7 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001f96: 4b30 ldr r3, [pc, #192] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001f98: 681b ldr r3, [r3, #0]
8001f9a: f003 0302 and.w r3, r3, #2
8001f9e: 2b00 cmp r3, #0
8001fa0: d0f0 beq.n 8001f84 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001fa2: 4b2d ldr r3, [pc, #180] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001fa4: 681b ldr r3, [r3, #0]
8001fa6: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8001faa: 687b ldr r3, [r7, #4]
8001fac: 691b ldr r3, [r3, #16]
8001fae: 00db lsls r3, r3, #3
8001fb0: 4929 ldr r1, [pc, #164] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001fb2: 4313 orrs r3, r2
8001fb4: 600b str r3, [r1, #0]
8001fb6: e018 b.n 8001fea <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001fb8: 4b27 ldr r3, [pc, #156] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001fba: 681b ldr r3, [r3, #0]
8001fbc: 4a26 ldr r2, [pc, #152] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001fbe: f023 0301 bic.w r3, r3, #1
8001fc2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001fc4: f7fe ff2a bl 8000e1c <HAL_GetTick>
8001fc8: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001fca: e008 b.n 8001fde <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8001fcc: f7fe ff26 bl 8000e1c <HAL_GetTick>
8001fd0: 4602 mov r2, r0
8001fd2: 693b ldr r3, [r7, #16]
8001fd4: 1ad3 subs r3, r2, r3
8001fd6: 2b02 cmp r3, #2
8001fd8: d901 bls.n 8001fde <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8001fda: 2303 movs r3, #3
8001fdc: e1a3 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001fde: 4b1e ldr r3, [pc, #120] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8001fe0: 681b ldr r3, [r3, #0]
8001fe2: f003 0302 and.w r3, r3, #2
8001fe6: 2b00 cmp r3, #0
8001fe8: d1f0 bne.n 8001fcc <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001fea: 687b ldr r3, [r7, #4]
8001fec: 681b ldr r3, [r3, #0]
8001fee: f003 0308 and.w r3, r3, #8
8001ff2: 2b00 cmp r3, #0
8001ff4: d038 beq.n 8002068 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 695b ldr r3, [r3, #20]
8001ffa: 2b00 cmp r3, #0
8001ffc: d019 beq.n 8002032 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001ffe: 4b16 ldr r3, [pc, #88] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8002000: 6f5b ldr r3, [r3, #116] @ 0x74
8002002: 4a15 ldr r2, [pc, #84] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8002004: f043 0301 orr.w r3, r3, #1
8002008: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
800200a: f7fe ff07 bl 8000e1c <HAL_GetTick>
800200e: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002010: e008 b.n 8002024 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002012: f7fe ff03 bl 8000e1c <HAL_GetTick>
8002016: 4602 mov r2, r0
8002018: 693b ldr r3, [r7, #16]
800201a: 1ad3 subs r3, r2, r3
800201c: 2b02 cmp r3, #2
800201e: d901 bls.n 8002024 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8002020: 2303 movs r3, #3
8002022: e180 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002024: 4b0c ldr r3, [pc, #48] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8002026: 6f5b ldr r3, [r3, #116] @ 0x74
8002028: f003 0302 and.w r3, r3, #2
800202c: 2b00 cmp r3, #0
800202e: d0f0 beq.n 8002012 <HAL_RCC_OscConfig+0x23a>
8002030: e01a b.n 8002068 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002032: 4b09 ldr r3, [pc, #36] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8002034: 6f5b ldr r3, [r3, #116] @ 0x74
8002036: 4a08 ldr r2, [pc, #32] @ (8002058 <HAL_RCC_OscConfig+0x280>)
8002038: f023 0301 bic.w r3, r3, #1
800203c: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
800203e: f7fe feed bl 8000e1c <HAL_GetTick>
8002042: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002044: e00a b.n 800205c <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8002046: f7fe fee9 bl 8000e1c <HAL_GetTick>
800204a: 4602 mov r2, r0
800204c: 693b ldr r3, [r7, #16]
800204e: 1ad3 subs r3, r2, r3
8002050: 2b02 cmp r3, #2
8002052: d903 bls.n 800205c <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8002054: 2303 movs r3, #3
8002056: e166 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
8002058: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800205c: 4b92 ldr r3, [pc, #584] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800205e: 6f5b ldr r3, [r3, #116] @ 0x74
8002060: f003 0302 and.w r3, r3, #2
8002064: 2b00 cmp r3, #0
8002066: d1ee bne.n 8002046 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002068: 687b ldr r3, [r7, #4]
800206a: 681b ldr r3, [r3, #0]
800206c: f003 0304 and.w r3, r3, #4
8002070: 2b00 cmp r3, #0
8002072: f000 80a4 beq.w 80021be <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8002076: 4b8c ldr r3, [pc, #560] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002078: 6c1b ldr r3, [r3, #64] @ 0x40
800207a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800207e: 2b00 cmp r3, #0
8002080: d10d bne.n 800209e <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002082: 4b89 ldr r3, [pc, #548] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002084: 6c1b ldr r3, [r3, #64] @ 0x40
8002086: 4a88 ldr r2, [pc, #544] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002088: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800208c: 6413 str r3, [r2, #64] @ 0x40
800208e: 4b86 ldr r3, [pc, #536] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002090: 6c1b ldr r3, [r3, #64] @ 0x40
8002092: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002096: 60bb str r3, [r7, #8]
8002098: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800209a: 2301 movs r3, #1
800209c: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
800209e: 4b83 ldr r3, [pc, #524] @ (80022ac <HAL_RCC_OscConfig+0x4d4>)
80020a0: 681b ldr r3, [r3, #0]
80020a2: f403 7380 and.w r3, r3, #256 @ 0x100
80020a6: 2b00 cmp r3, #0
80020a8: d118 bne.n 80020dc <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
80020aa: 4b80 ldr r3, [pc, #512] @ (80022ac <HAL_RCC_OscConfig+0x4d4>)
80020ac: 681b ldr r3, [r3, #0]
80020ae: 4a7f ldr r2, [pc, #508] @ (80022ac <HAL_RCC_OscConfig+0x4d4>)
80020b0: f443 7380 orr.w r3, r3, #256 @ 0x100
80020b4: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80020b6: f7fe feb1 bl 8000e1c <HAL_GetTick>
80020ba: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80020bc: e008 b.n 80020d0 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80020be: f7fe fead bl 8000e1c <HAL_GetTick>
80020c2: 4602 mov r2, r0
80020c4: 693b ldr r3, [r7, #16]
80020c6: 1ad3 subs r3, r2, r3
80020c8: 2b64 cmp r3, #100 @ 0x64
80020ca: d901 bls.n 80020d0 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
80020cc: 2303 movs r3, #3
80020ce: e12a b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80020d0: 4b76 ldr r3, [pc, #472] @ (80022ac <HAL_RCC_OscConfig+0x4d4>)
80020d2: 681b ldr r3, [r3, #0]
80020d4: f403 7380 and.w r3, r3, #256 @ 0x100
80020d8: 2b00 cmp r3, #0
80020da: d0f0 beq.n 80020be <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80020dc: 687b ldr r3, [r7, #4]
80020de: 689b ldr r3, [r3, #8]
80020e0: 2b01 cmp r3, #1
80020e2: d106 bne.n 80020f2 <HAL_RCC_OscConfig+0x31a>
80020e4: 4b70 ldr r3, [pc, #448] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80020e6: 6f1b ldr r3, [r3, #112] @ 0x70
80020e8: 4a6f ldr r2, [pc, #444] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80020ea: f043 0301 orr.w r3, r3, #1
80020ee: 6713 str r3, [r2, #112] @ 0x70
80020f0: e02d b.n 800214e <HAL_RCC_OscConfig+0x376>
80020f2: 687b ldr r3, [r7, #4]
80020f4: 689b ldr r3, [r3, #8]
80020f6: 2b00 cmp r3, #0
80020f8: d10c bne.n 8002114 <HAL_RCC_OscConfig+0x33c>
80020fa: 4b6b ldr r3, [pc, #428] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80020fc: 6f1b ldr r3, [r3, #112] @ 0x70
80020fe: 4a6a ldr r2, [pc, #424] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002100: f023 0301 bic.w r3, r3, #1
8002104: 6713 str r3, [r2, #112] @ 0x70
8002106: 4b68 ldr r3, [pc, #416] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002108: 6f1b ldr r3, [r3, #112] @ 0x70
800210a: 4a67 ldr r2, [pc, #412] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800210c: f023 0304 bic.w r3, r3, #4
8002110: 6713 str r3, [r2, #112] @ 0x70
8002112: e01c b.n 800214e <HAL_RCC_OscConfig+0x376>
8002114: 687b ldr r3, [r7, #4]
8002116: 689b ldr r3, [r3, #8]
8002118: 2b05 cmp r3, #5
800211a: d10c bne.n 8002136 <HAL_RCC_OscConfig+0x35e>
800211c: 4b62 ldr r3, [pc, #392] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800211e: 6f1b ldr r3, [r3, #112] @ 0x70
8002120: 4a61 ldr r2, [pc, #388] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002122: f043 0304 orr.w r3, r3, #4
8002126: 6713 str r3, [r2, #112] @ 0x70
8002128: 4b5f ldr r3, [pc, #380] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800212a: 6f1b ldr r3, [r3, #112] @ 0x70
800212c: 4a5e ldr r2, [pc, #376] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800212e: f043 0301 orr.w r3, r3, #1
8002132: 6713 str r3, [r2, #112] @ 0x70
8002134: e00b b.n 800214e <HAL_RCC_OscConfig+0x376>
8002136: 4b5c ldr r3, [pc, #368] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002138: 6f1b ldr r3, [r3, #112] @ 0x70
800213a: 4a5b ldr r2, [pc, #364] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800213c: f023 0301 bic.w r3, r3, #1
8002140: 6713 str r3, [r2, #112] @ 0x70
8002142: 4b59 ldr r3, [pc, #356] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002144: 6f1b ldr r3, [r3, #112] @ 0x70
8002146: 4a58 ldr r2, [pc, #352] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002148: f023 0304 bic.w r3, r3, #4
800214c: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
800214e: 687b ldr r3, [r7, #4]
8002150: 689b ldr r3, [r3, #8]
8002152: 2b00 cmp r3, #0
8002154: d015 beq.n 8002182 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002156: f7fe fe61 bl 8000e1c <HAL_GetTick>
800215a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800215c: e00a b.n 8002174 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800215e: f7fe fe5d bl 8000e1c <HAL_GetTick>
8002162: 4602 mov r2, r0
8002164: 693b ldr r3, [r7, #16]
8002166: 1ad3 subs r3, r2, r3
8002168: f241 3288 movw r2, #5000 @ 0x1388
800216c: 4293 cmp r3, r2
800216e: d901 bls.n 8002174 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8002170: 2303 movs r3, #3
8002172: e0d8 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002174: 4b4c ldr r3, [pc, #304] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002176: 6f1b ldr r3, [r3, #112] @ 0x70
8002178: f003 0302 and.w r3, r3, #2
800217c: 2b00 cmp r3, #0
800217e: d0ee beq.n 800215e <HAL_RCC_OscConfig+0x386>
8002180: e014 b.n 80021ac <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002182: f7fe fe4b bl 8000e1c <HAL_GetTick>
8002186: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002188: e00a b.n 80021a0 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800218a: f7fe fe47 bl 8000e1c <HAL_GetTick>
800218e: 4602 mov r2, r0
8002190: 693b ldr r3, [r7, #16]
8002192: 1ad3 subs r3, r2, r3
8002194: f241 3288 movw r2, #5000 @ 0x1388
8002198: 4293 cmp r3, r2
800219a: d901 bls.n 80021a0 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
800219c: 2303 movs r3, #3
800219e: e0c2 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80021a0: 4b41 ldr r3, [pc, #260] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021a2: 6f1b ldr r3, [r3, #112] @ 0x70
80021a4: f003 0302 and.w r3, r3, #2
80021a8: 2b00 cmp r3, #0
80021aa: d1ee bne.n 800218a <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80021ac: 7dfb ldrb r3, [r7, #23]
80021ae: 2b01 cmp r3, #1
80021b0: d105 bne.n 80021be <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
80021b2: 4b3d ldr r3, [pc, #244] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021b4: 6c1b ldr r3, [r3, #64] @ 0x40
80021b6: 4a3c ldr r2, [pc, #240] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021b8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80021bc: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80021be: 687b ldr r3, [r7, #4]
80021c0: 699b ldr r3, [r3, #24]
80021c2: 2b00 cmp r3, #0
80021c4: f000 80ae beq.w 8002324 <HAL_RCC_OscConfig+0x54c>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80021c8: 4b37 ldr r3, [pc, #220] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021ca: 689b ldr r3, [r3, #8]
80021cc: f003 030c and.w r3, r3, #12
80021d0: 2b08 cmp r3, #8
80021d2: d06d beq.n 80022b0 <HAL_RCC_OscConfig+0x4d8>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80021d4: 687b ldr r3, [r7, #4]
80021d6: 699b ldr r3, [r3, #24]
80021d8: 2b02 cmp r3, #2
80021da: d14b bne.n 8002274 <HAL_RCC_OscConfig+0x49c>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80021dc: 4b32 ldr r3, [pc, #200] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021de: 681b ldr r3, [r3, #0]
80021e0: 4a31 ldr r2, [pc, #196] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
80021e2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80021e6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80021e8: f7fe fe18 bl 8000e1c <HAL_GetTick>
80021ec: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80021ee: e008 b.n 8002202 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80021f0: f7fe fe14 bl 8000e1c <HAL_GetTick>
80021f4: 4602 mov r2, r0
80021f6: 693b ldr r3, [r7, #16]
80021f8: 1ad3 subs r3, r2, r3
80021fa: 2b02 cmp r3, #2
80021fc: d901 bls.n 8002202 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
80021fe: 2303 movs r3, #3
8002200: e091 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002202: 4b29 ldr r3, [pc, #164] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002204: 681b ldr r3, [r3, #0]
8002206: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800220a: 2b00 cmp r3, #0
800220c: d1f0 bne.n 80021f0 <HAL_RCC_OscConfig+0x418>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined (RCC_PLLCFGR_PLLR)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
800220e: 687b ldr r3, [r7, #4]
8002210: 69da ldr r2, [r3, #28]
8002212: 687b ldr r3, [r7, #4]
8002214: 6a1b ldr r3, [r3, #32]
8002216: 431a orrs r2, r3
8002218: 687b ldr r3, [r7, #4]
800221a: 6a5b ldr r3, [r3, #36] @ 0x24
800221c: 019b lsls r3, r3, #6
800221e: 431a orrs r2, r3
8002220: 687b ldr r3, [r7, #4]
8002222: 6a9b ldr r3, [r3, #40] @ 0x28
8002224: 085b lsrs r3, r3, #1
8002226: 3b01 subs r3, #1
8002228: 041b lsls r3, r3, #16
800222a: 431a orrs r2, r3
800222c: 687b ldr r3, [r7, #4]
800222e: 6adb ldr r3, [r3, #44] @ 0x2c
8002230: 061b lsls r3, r3, #24
8002232: 431a orrs r2, r3
8002234: 687b ldr r3, [r7, #4]
8002236: 6b1b ldr r3, [r3, #48] @ 0x30
8002238: 071b lsls r3, r3, #28
800223a: 491b ldr r1, [pc, #108] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800223c: 4313 orrs r3, r2
800223e: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002240: 4b19 ldr r3, [pc, #100] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002242: 681b ldr r3, [r3, #0]
8002244: 4a18 ldr r2, [pc, #96] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002246: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
800224a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800224c: f7fe fde6 bl 8000e1c <HAL_GetTick>
8002250: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002252: e008 b.n 8002266 <HAL_RCC_OscConfig+0x48e>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002254: f7fe fde2 bl 8000e1c <HAL_GetTick>
8002258: 4602 mov r2, r0
800225a: 693b ldr r3, [r7, #16]
800225c: 1ad3 subs r3, r2, r3
800225e: 2b02 cmp r3, #2
8002260: d901 bls.n 8002266 <HAL_RCC_OscConfig+0x48e>
{
return HAL_TIMEOUT;
8002262: 2303 movs r3, #3
8002264: e05f b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002266: 4b10 ldr r3, [pc, #64] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002268: 681b ldr r3, [r3, #0]
800226a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800226e: 2b00 cmp r3, #0
8002270: d0f0 beq.n 8002254 <HAL_RCC_OscConfig+0x47c>
8002272: e057 b.n 8002324 <HAL_RCC_OscConfig+0x54c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002274: 4b0c ldr r3, [pc, #48] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
8002276: 681b ldr r3, [r3, #0]
8002278: 4a0b ldr r2, [pc, #44] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800227a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800227e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002280: f7fe fdcc bl 8000e1c <HAL_GetTick>
8002284: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002286: e008 b.n 800229a <HAL_RCC_OscConfig+0x4c2>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8002288: f7fe fdc8 bl 8000e1c <HAL_GetTick>
800228c: 4602 mov r2, r0
800228e: 693b ldr r3, [r7, #16]
8002290: 1ad3 subs r3, r2, r3
8002292: 2b02 cmp r3, #2
8002294: d901 bls.n 800229a <HAL_RCC_OscConfig+0x4c2>
{
return HAL_TIMEOUT;
8002296: 2303 movs r3, #3
8002298: e045 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800229a: 4b03 ldr r3, [pc, #12] @ (80022a8 <HAL_RCC_OscConfig+0x4d0>)
800229c: 681b ldr r3, [r3, #0]
800229e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80022a2: 2b00 cmp r3, #0
80022a4: d1f0 bne.n 8002288 <HAL_RCC_OscConfig+0x4b0>
80022a6: e03d b.n 8002324 <HAL_RCC_OscConfig+0x54c>
80022a8: 40023800 .word 0x40023800
80022ac: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
80022b0: 4b1f ldr r3, [pc, #124] @ (8002330 <HAL_RCC_OscConfig+0x558>)
80022b2: 685b ldr r3, [r3, #4]
80022b4: 60fb str r3, [r7, #12]
#if defined (RCC_PLLCFGR_PLLR)
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80022b6: 687b ldr r3, [r7, #4]
80022b8: 699b ldr r3, [r3, #24]
80022ba: 2b01 cmp r3, #1
80022bc: d030 beq.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80022be: 68fb ldr r3, [r7, #12]
80022c0: f403 0280 and.w r2, r3, #4194304 @ 0x400000
80022c4: 687b ldr r3, [r7, #4]
80022c6: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80022c8: 429a cmp r2, r3
80022ca: d129 bne.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80022cc: 68fb ldr r3, [r7, #12]
80022ce: f003 023f and.w r2, r3, #63 @ 0x3f
80022d2: 687b ldr r3, [r7, #4]
80022d4: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80022d6: 429a cmp r2, r3
80022d8: d122 bne.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80022da: 68fa ldr r2, [r7, #12]
80022dc: f647 73c0 movw r3, #32704 @ 0x7fc0
80022e0: 4013 ands r3, r2
80022e2: 687a ldr r2, [r7, #4]
80022e4: 6a52 ldr r2, [r2, #36] @ 0x24
80022e6: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80022e8: 4293 cmp r3, r2
80022ea: d119 bne.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
80022ec: 68fb ldr r3, [r7, #12]
80022ee: f403 3240 and.w r2, r3, #196608 @ 0x30000
80022f2: 687b ldr r3, [r7, #4]
80022f4: 6a9b ldr r3, [r3, #40] @ 0x28
80022f6: 085b lsrs r3, r3, #1
80022f8: 3b01 subs r3, #1
80022fa: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80022fc: 429a cmp r2, r3
80022fe: d10f bne.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
8002300: 68fb ldr r3, [r7, #12]
8002302: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
8002306: 687b ldr r3, [r7, #4]
8002308: 6adb ldr r3, [r3, #44] @ 0x2c
800230a: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
800230c: 429a cmp r2, r3
800230e: d107 bne.n 8002320 <HAL_RCC_OscConfig+0x548>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
8002310: 68fb ldr r3, [r7, #12]
8002312: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
8002316: 687b ldr r3, [r7, #4]
8002318: 6b1b ldr r3, [r3, #48] @ 0x30
800231a: 071b lsls r3, r3, #28
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
800231c: 429a cmp r2, r3
800231e: d001 beq.n 8002324 <HAL_RCC_OscConfig+0x54c>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{
return HAL_ERROR;
8002320: 2301 movs r3, #1
8002322: e000 b.n 8002326 <HAL_RCC_OscConfig+0x54e>
}
}
}
return HAL_OK;
8002324: 2300 movs r3, #0
}
8002326: 4618 mov r0, r3
8002328: 3718 adds r7, #24
800232a: 46bd mov sp, r7
800232c: bd80 pop {r7, pc}
800232e: bf00 nop
8002330: 40023800 .word 0x40023800
08002334 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002334: b580 push {r7, lr}
8002336: b084 sub sp, #16
8002338: af00 add r7, sp, #0
800233a: 6078 str r0, [r7, #4]
800233c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
800233e: 2300 movs r3, #0
8002340: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8002342: 687b ldr r3, [r7, #4]
8002344: 2b00 cmp r3, #0
8002346: d101 bne.n 800234c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002348: 2301 movs r3, #1
800234a: e0d0 b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800234c: 4b6a ldr r3, [pc, #424] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
800234e: 681b ldr r3, [r3, #0]
8002350: f003 030f and.w r3, r3, #15
8002354: 683a ldr r2, [r7, #0]
8002356: 429a cmp r2, r3
8002358: d910 bls.n 800237c <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800235a: 4b67 ldr r3, [pc, #412] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
800235c: 681b ldr r3, [r3, #0]
800235e: f023 020f bic.w r2, r3, #15
8002362: 4965 ldr r1, [pc, #404] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
8002364: 683b ldr r3, [r7, #0]
8002366: 4313 orrs r3, r2
8002368: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800236a: 4b63 ldr r3, [pc, #396] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
800236c: 681b ldr r3, [r3, #0]
800236e: f003 030f and.w r3, r3, #15
8002372: 683a ldr r2, [r7, #0]
8002374: 429a cmp r2, r3
8002376: d001 beq.n 800237c <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002378: 2301 movs r3, #1
800237a: e0b8 b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800237c: 687b ldr r3, [r7, #4]
800237e: 681b ldr r3, [r3, #0]
8002380: f003 0302 and.w r3, r3, #2
8002384: 2b00 cmp r3, #0
8002386: d020 beq.n 80023ca <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002388: 687b ldr r3, [r7, #4]
800238a: 681b ldr r3, [r3, #0]
800238c: f003 0304 and.w r3, r3, #4
8002390: 2b00 cmp r3, #0
8002392: d005 beq.n 80023a0 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002394: 4b59 ldr r3, [pc, #356] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002396: 689b ldr r3, [r3, #8]
8002398: 4a58 ldr r2, [pc, #352] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
800239a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
800239e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80023a0: 687b ldr r3, [r7, #4]
80023a2: 681b ldr r3, [r3, #0]
80023a4: f003 0308 and.w r3, r3, #8
80023a8: 2b00 cmp r3, #0
80023aa: d005 beq.n 80023b8 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80023ac: 4b53 ldr r3, [pc, #332] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023ae: 689b ldr r3, [r3, #8]
80023b0: 4a52 ldr r2, [pc, #328] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023b2: f443 4360 orr.w r3, r3, #57344 @ 0xe000
80023b6: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80023b8: 4b50 ldr r3, [pc, #320] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023ba: 689b ldr r3, [r3, #8]
80023bc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
80023c0: 687b ldr r3, [r7, #4]
80023c2: 689b ldr r3, [r3, #8]
80023c4: 494d ldr r1, [pc, #308] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023c6: 4313 orrs r3, r2
80023c8: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80023ca: 687b ldr r3, [r7, #4]
80023cc: 681b ldr r3, [r3, #0]
80023ce: f003 0301 and.w r3, r3, #1
80023d2: 2b00 cmp r3, #0
80023d4: d040 beq.n 8002458 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80023d6: 687b ldr r3, [r7, #4]
80023d8: 685b ldr r3, [r3, #4]
80023da: 2b01 cmp r3, #1
80023dc: d107 bne.n 80023ee <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80023de: 4b47 ldr r3, [pc, #284] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023e0: 681b ldr r3, [r3, #0]
80023e2: f403 3300 and.w r3, r3, #131072 @ 0x20000
80023e6: 2b00 cmp r3, #0
80023e8: d115 bne.n 8002416 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80023ea: 2301 movs r3, #1
80023ec: e07f b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80023ee: 687b ldr r3, [r7, #4]
80023f0: 685b ldr r3, [r3, #4]
80023f2: 2b02 cmp r3, #2
80023f4: d107 bne.n 8002406 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80023f6: 4b41 ldr r3, [pc, #260] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80023f8: 681b ldr r3, [r3, #0]
80023fa: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80023fe: 2b00 cmp r3, #0
8002400: d109 bne.n 8002416 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002402: 2301 movs r3, #1
8002404: e073 b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002406: 4b3d ldr r3, [pc, #244] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002408: 681b ldr r3, [r3, #0]
800240a: f003 0302 and.w r3, r3, #2
800240e: 2b00 cmp r3, #0
8002410: d101 bne.n 8002416 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8002412: 2301 movs r3, #1
8002414: e06b b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002416: 4b39 ldr r3, [pc, #228] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002418: 689b ldr r3, [r3, #8]
800241a: f023 0203 bic.w r2, r3, #3
800241e: 687b ldr r3, [r7, #4]
8002420: 685b ldr r3, [r3, #4]
8002422: 4936 ldr r1, [pc, #216] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002424: 4313 orrs r3, r2
8002426: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002428: f7fe fcf8 bl 8000e1c <HAL_GetTick>
800242c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800242e: e00a b.n 8002446 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002430: f7fe fcf4 bl 8000e1c <HAL_GetTick>
8002434: 4602 mov r2, r0
8002436: 68fb ldr r3, [r7, #12]
8002438: 1ad3 subs r3, r2, r3
800243a: f241 3288 movw r2, #5000 @ 0x1388
800243e: 4293 cmp r3, r2
8002440: d901 bls.n 8002446 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8002442: 2303 movs r3, #3
8002444: e053 b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002446: 4b2d ldr r3, [pc, #180] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002448: 689b ldr r3, [r3, #8]
800244a: f003 020c and.w r2, r3, #12
800244e: 687b ldr r3, [r7, #4]
8002450: 685b ldr r3, [r3, #4]
8002452: 009b lsls r3, r3, #2
8002454: 429a cmp r2, r3
8002456: d1eb bne.n 8002430 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002458: 4b27 ldr r3, [pc, #156] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
800245a: 681b ldr r3, [r3, #0]
800245c: f003 030f and.w r3, r3, #15
8002460: 683a ldr r2, [r7, #0]
8002462: 429a cmp r2, r3
8002464: d210 bcs.n 8002488 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002466: 4b24 ldr r3, [pc, #144] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
8002468: 681b ldr r3, [r3, #0]
800246a: f023 020f bic.w r2, r3, #15
800246e: 4922 ldr r1, [pc, #136] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
8002470: 683b ldr r3, [r7, #0]
8002472: 4313 orrs r3, r2
8002474: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002476: 4b20 ldr r3, [pc, #128] @ (80024f8 <HAL_RCC_ClockConfig+0x1c4>)
8002478: 681b ldr r3, [r3, #0]
800247a: f003 030f and.w r3, r3, #15
800247e: 683a ldr r2, [r7, #0]
8002480: 429a cmp r2, r3
8002482: d001 beq.n 8002488 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8002484: 2301 movs r3, #1
8002486: e032 b.n 80024ee <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002488: 687b ldr r3, [r7, #4]
800248a: 681b ldr r3, [r3, #0]
800248c: f003 0304 and.w r3, r3, #4
8002490: 2b00 cmp r3, #0
8002492: d008 beq.n 80024a6 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002494: 4b19 ldr r3, [pc, #100] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
8002496: 689b ldr r3, [r3, #8]
8002498: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
800249c: 687b ldr r3, [r7, #4]
800249e: 68db ldr r3, [r3, #12]
80024a0: 4916 ldr r1, [pc, #88] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80024a2: 4313 orrs r3, r2
80024a4: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80024a6: 687b ldr r3, [r7, #4]
80024a8: 681b ldr r3, [r3, #0]
80024aa: f003 0308 and.w r3, r3, #8
80024ae: 2b00 cmp r3, #0
80024b0: d009 beq.n 80024c6 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
80024b2: 4b12 ldr r3, [pc, #72] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80024b4: 689b ldr r3, [r3, #8]
80024b6: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80024ba: 687b ldr r3, [r7, #4]
80024bc: 691b ldr r3, [r3, #16]
80024be: 00db lsls r3, r3, #3
80024c0: 490e ldr r1, [pc, #56] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80024c2: 4313 orrs r3, r2
80024c4: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80024c6: f000 f821 bl 800250c <HAL_RCC_GetSysClockFreq>
80024ca: 4602 mov r2, r0
80024cc: 4b0b ldr r3, [pc, #44] @ (80024fc <HAL_RCC_ClockConfig+0x1c8>)
80024ce: 689b ldr r3, [r3, #8]
80024d0: 091b lsrs r3, r3, #4
80024d2: f003 030f and.w r3, r3, #15
80024d6: 490a ldr r1, [pc, #40] @ (8002500 <HAL_RCC_ClockConfig+0x1cc>)
80024d8: 5ccb ldrb r3, [r1, r3]
80024da: fa22 f303 lsr.w r3, r2, r3
80024de: 4a09 ldr r2, [pc, #36] @ (8002504 <HAL_RCC_ClockConfig+0x1d0>)
80024e0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
80024e2: 4b09 ldr r3, [pc, #36] @ (8002508 <HAL_RCC_ClockConfig+0x1d4>)
80024e4: 681b ldr r3, [r3, #0]
80024e6: 4618 mov r0, r3
80024e8: f7fe fc54 bl 8000d94 <HAL_InitTick>
return HAL_OK;
80024ec: 2300 movs r3, #0
}
80024ee: 4618 mov r0, r3
80024f0: 3710 adds r7, #16
80024f2: 46bd mov sp, r7
80024f4: bd80 pop {r7, pc}
80024f6: bf00 nop
80024f8: 40023c00 .word 0x40023c00
80024fc: 40023800 .word 0x40023800
8002500: 08003fc8 .word 0x08003fc8
8002504: 20000000 .word 0x20000000
8002508: 20000004 .word 0x20000004
0800250c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800250c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002510: b094 sub sp, #80 @ 0x50
8002512: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8002514: 2300 movs r3, #0
8002516: 647b str r3, [r7, #68] @ 0x44
8002518: 2300 movs r3, #0
800251a: 64fb str r3, [r7, #76] @ 0x4c
800251c: 2300 movs r3, #0
800251e: 643b str r3, [r7, #64] @ 0x40
uint32_t sysclockfreq = 0;
8002520: 2300 movs r3, #0
8002522: 64bb str r3, [r7, #72] @ 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8002524: 4b79 ldr r3, [pc, #484] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
8002526: 689b ldr r3, [r3, #8]
8002528: f003 030c and.w r3, r3, #12
800252c: 2b08 cmp r3, #8
800252e: d00d beq.n 800254c <HAL_RCC_GetSysClockFreq+0x40>
8002530: 2b08 cmp r3, #8
8002532: f200 80e1 bhi.w 80026f8 <HAL_RCC_GetSysClockFreq+0x1ec>
8002536: 2b00 cmp r3, #0
8002538: d002 beq.n 8002540 <HAL_RCC_GetSysClockFreq+0x34>
800253a: 2b04 cmp r3, #4
800253c: d003 beq.n 8002546 <HAL_RCC_GetSysClockFreq+0x3a>
800253e: e0db b.n 80026f8 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002540: 4b73 ldr r3, [pc, #460] @ (8002710 <HAL_RCC_GetSysClockFreq+0x204>)
8002542: 64bb str r3, [r7, #72] @ 0x48
break;
8002544: e0db b.n 80026fe <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8002546: 4b73 ldr r3, [pc, #460] @ (8002714 <HAL_RCC_GetSysClockFreq+0x208>)
8002548: 64bb str r3, [r7, #72] @ 0x48
break;
800254a: e0d8 b.n 80026fe <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
800254c: 4b6f ldr r3, [pc, #444] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
800254e: 685b ldr r3, [r3, #4]
8002550: f003 033f and.w r3, r3, #63 @ 0x3f
8002554: 647b str r3, [r7, #68] @ 0x44
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8002556: 4b6d ldr r3, [pc, #436] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
8002558: 685b ldr r3, [r3, #4]
800255a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800255e: 2b00 cmp r3, #0
8002560: d063 beq.n 800262a <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002562: 4b6a ldr r3, [pc, #424] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
8002564: 685b ldr r3, [r3, #4]
8002566: 099b lsrs r3, r3, #6
8002568: 2200 movs r2, #0
800256a: 63bb str r3, [r7, #56] @ 0x38
800256c: 63fa str r2, [r7, #60] @ 0x3c
800256e: 6bbb ldr r3, [r7, #56] @ 0x38
8002570: f3c3 0308 ubfx r3, r3, #0, #9
8002574: 633b str r3, [r7, #48] @ 0x30
8002576: 2300 movs r3, #0
8002578: 637b str r3, [r7, #52] @ 0x34
800257a: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
800257e: 4622 mov r2, r4
8002580: 462b mov r3, r5
8002582: f04f 0000 mov.w r0, #0
8002586: f04f 0100 mov.w r1, #0
800258a: 0159 lsls r1, r3, #5
800258c: ea41 61d2 orr.w r1, r1, r2, lsr #27
8002590: 0150 lsls r0, r2, #5
8002592: 4602 mov r2, r0
8002594: 460b mov r3, r1
8002596: 4621 mov r1, r4
8002598: 1a51 subs r1, r2, r1
800259a: 6139 str r1, [r7, #16]
800259c: 4629 mov r1, r5
800259e: eb63 0301 sbc.w r3, r3, r1
80025a2: 617b str r3, [r7, #20]
80025a4: f04f 0200 mov.w r2, #0
80025a8: f04f 0300 mov.w r3, #0
80025ac: e9d7 ab04 ldrd sl, fp, [r7, #16]
80025b0: 4659 mov r1, fp
80025b2: 018b lsls r3, r1, #6
80025b4: 4651 mov r1, sl
80025b6: ea43 6391 orr.w r3, r3, r1, lsr #26
80025ba: 4651 mov r1, sl
80025bc: 018a lsls r2, r1, #6
80025be: 4651 mov r1, sl
80025c0: ebb2 0801 subs.w r8, r2, r1
80025c4: 4659 mov r1, fp
80025c6: eb63 0901 sbc.w r9, r3, r1
80025ca: f04f 0200 mov.w r2, #0
80025ce: f04f 0300 mov.w r3, #0
80025d2: ea4f 03c9 mov.w r3, r9, lsl #3
80025d6: ea43 7358 orr.w r3, r3, r8, lsr #29
80025da: ea4f 02c8 mov.w r2, r8, lsl #3
80025de: 4690 mov r8, r2
80025e0: 4699 mov r9, r3
80025e2: 4623 mov r3, r4
80025e4: eb18 0303 adds.w r3, r8, r3
80025e8: 60bb str r3, [r7, #8]
80025ea: 462b mov r3, r5
80025ec: eb49 0303 adc.w r3, r9, r3
80025f0: 60fb str r3, [r7, #12]
80025f2: f04f 0200 mov.w r2, #0
80025f6: f04f 0300 mov.w r3, #0
80025fa: e9d7 4502 ldrd r4, r5, [r7, #8]
80025fe: 4629 mov r1, r5
8002600: 024b lsls r3, r1, #9
8002602: 4621 mov r1, r4
8002604: ea43 53d1 orr.w r3, r3, r1, lsr #23
8002608: 4621 mov r1, r4
800260a: 024a lsls r2, r1, #9
800260c: 4610 mov r0, r2
800260e: 4619 mov r1, r3
8002610: 6c7b ldr r3, [r7, #68] @ 0x44
8002612: 2200 movs r2, #0
8002614: 62bb str r3, [r7, #40] @ 0x28
8002616: 62fa str r2, [r7, #44] @ 0x2c
8002618: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
800261c: f7fd fe0c bl 8000238 <__aeabi_uldivmod>
8002620: 4602 mov r2, r0
8002622: 460b mov r3, r1
8002624: 4613 mov r3, r2
8002626: 64fb str r3, [r7, #76] @ 0x4c
8002628: e058 b.n 80026dc <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800262a: 4b38 ldr r3, [pc, #224] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
800262c: 685b ldr r3, [r3, #4]
800262e: 099b lsrs r3, r3, #6
8002630: 2200 movs r2, #0
8002632: 4618 mov r0, r3
8002634: 4611 mov r1, r2
8002636: f3c0 0308 ubfx r3, r0, #0, #9
800263a: 623b str r3, [r7, #32]
800263c: 2300 movs r3, #0
800263e: 627b str r3, [r7, #36] @ 0x24
8002640: e9d7 8908 ldrd r8, r9, [r7, #32]
8002644: 4642 mov r2, r8
8002646: 464b mov r3, r9
8002648: f04f 0000 mov.w r0, #0
800264c: f04f 0100 mov.w r1, #0
8002650: 0159 lsls r1, r3, #5
8002652: ea41 61d2 orr.w r1, r1, r2, lsr #27
8002656: 0150 lsls r0, r2, #5
8002658: 4602 mov r2, r0
800265a: 460b mov r3, r1
800265c: 4641 mov r1, r8
800265e: ebb2 0a01 subs.w sl, r2, r1
8002662: 4649 mov r1, r9
8002664: eb63 0b01 sbc.w fp, r3, r1
8002668: f04f 0200 mov.w r2, #0
800266c: f04f 0300 mov.w r3, #0
8002670: ea4f 138b mov.w r3, fp, lsl #6
8002674: ea43 639a orr.w r3, r3, sl, lsr #26
8002678: ea4f 128a mov.w r2, sl, lsl #6
800267c: ebb2 040a subs.w r4, r2, sl
8002680: eb63 050b sbc.w r5, r3, fp
8002684: f04f 0200 mov.w r2, #0
8002688: f04f 0300 mov.w r3, #0
800268c: 00eb lsls r3, r5, #3
800268e: ea43 7354 orr.w r3, r3, r4, lsr #29
8002692: 00e2 lsls r2, r4, #3
8002694: 4614 mov r4, r2
8002696: 461d mov r5, r3
8002698: 4643 mov r3, r8
800269a: 18e3 adds r3, r4, r3
800269c: 603b str r3, [r7, #0]
800269e: 464b mov r3, r9
80026a0: eb45 0303 adc.w r3, r5, r3
80026a4: 607b str r3, [r7, #4]
80026a6: f04f 0200 mov.w r2, #0
80026aa: f04f 0300 mov.w r3, #0
80026ae: e9d7 4500 ldrd r4, r5, [r7]
80026b2: 4629 mov r1, r5
80026b4: 028b lsls r3, r1, #10
80026b6: 4621 mov r1, r4
80026b8: ea43 5391 orr.w r3, r3, r1, lsr #22
80026bc: 4621 mov r1, r4
80026be: 028a lsls r2, r1, #10
80026c0: 4610 mov r0, r2
80026c2: 4619 mov r1, r3
80026c4: 6c7b ldr r3, [r7, #68] @ 0x44
80026c6: 2200 movs r2, #0
80026c8: 61bb str r3, [r7, #24]
80026ca: 61fa str r2, [r7, #28]
80026cc: e9d7 2306 ldrd r2, r3, [r7, #24]
80026d0: f7fd fdb2 bl 8000238 <__aeabi_uldivmod>
80026d4: 4602 mov r2, r0
80026d6: 460b mov r3, r1
80026d8: 4613 mov r3, r2
80026da: 64fb str r3, [r7, #76] @ 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
80026dc: 4b0b ldr r3, [pc, #44] @ (800270c <HAL_RCC_GetSysClockFreq+0x200>)
80026de: 685b ldr r3, [r3, #4]
80026e0: 0c1b lsrs r3, r3, #16
80026e2: f003 0303 and.w r3, r3, #3
80026e6: 3301 adds r3, #1
80026e8: 005b lsls r3, r3, #1
80026ea: 643b str r3, [r7, #64] @ 0x40
sysclockfreq = pllvco / pllp;
80026ec: 6cfa ldr r2, [r7, #76] @ 0x4c
80026ee: 6c3b ldr r3, [r7, #64] @ 0x40
80026f0: fbb2 f3f3 udiv r3, r2, r3
80026f4: 64bb str r3, [r7, #72] @ 0x48
break;
80026f6: e002 b.n 80026fe <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
80026f8: 4b05 ldr r3, [pc, #20] @ (8002710 <HAL_RCC_GetSysClockFreq+0x204>)
80026fa: 64bb str r3, [r7, #72] @ 0x48
break;
80026fc: bf00 nop
}
}
return sysclockfreq;
80026fe: 6cbb ldr r3, [r7, #72] @ 0x48
}
8002700: 4618 mov r0, r3
8002702: 3750 adds r7, #80 @ 0x50
8002704: 46bd mov sp, r7
8002706: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
800270a: bf00 nop
800270c: 40023800 .word 0x40023800
8002710: 00f42400 .word 0x00f42400
8002714: 007a1200 .word 0x007a1200
08002718 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002718: b480 push {r7}
800271a: af00 add r7, sp, #0
return SystemCoreClock;
800271c: 4b03 ldr r3, [pc, #12] @ (800272c <HAL_RCC_GetHCLKFreq+0x14>)
800271e: 681b ldr r3, [r3, #0]
}
8002720: 4618 mov r0, r3
8002722: 46bd mov sp, r7
8002724: f85d 7b04 ldr.w r7, [sp], #4
8002728: 4770 bx lr
800272a: bf00 nop
800272c: 20000000 .word 0x20000000
08002730 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002730: b580 push {r7, lr}
8002732: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8002734: f7ff fff0 bl 8002718 <HAL_RCC_GetHCLKFreq>
8002738: 4602 mov r2, r0
800273a: 4b05 ldr r3, [pc, #20] @ (8002750 <HAL_RCC_GetPCLK1Freq+0x20>)
800273c: 689b ldr r3, [r3, #8]
800273e: 0a9b lsrs r3, r3, #10
8002740: f003 0307 and.w r3, r3, #7
8002744: 4903 ldr r1, [pc, #12] @ (8002754 <HAL_RCC_GetPCLK1Freq+0x24>)
8002746: 5ccb ldrb r3, [r1, r3]
8002748: fa22 f303 lsr.w r3, r2, r3
}
800274c: 4618 mov r0, r3
800274e: bd80 pop {r7, pc}
8002750: 40023800 .word 0x40023800
8002754: 08003fd8 .word 0x08003fd8
08002758 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002758: b580 push {r7, lr}
800275a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
800275c: f7ff ffdc bl 8002718 <HAL_RCC_GetHCLKFreq>
8002760: 4602 mov r2, r0
8002762: 4b05 ldr r3, [pc, #20] @ (8002778 <HAL_RCC_GetPCLK2Freq+0x20>)
8002764: 689b ldr r3, [r3, #8]
8002766: 0b5b lsrs r3, r3, #13
8002768: f003 0307 and.w r3, r3, #7
800276c: 4903 ldr r1, [pc, #12] @ (800277c <HAL_RCC_GetPCLK2Freq+0x24>)
800276e: 5ccb ldrb r3, [r1, r3]
8002770: fa22 f303 lsr.w r3, r2, r3
}
8002774: 4618 mov r0, r3
8002776: bd80 pop {r7, pc}
8002778: 40023800 .word 0x40023800
800277c: 08003fd8 .word 0x08003fd8
08002780 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002780: b580 push {r7, lr}
8002782: b088 sub sp, #32
8002784: af00 add r7, sp, #0
8002786: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8002788: 2300 movs r3, #0
800278a: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
800278c: 2300 movs r3, #0
800278e: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
8002790: 2300 movs r3, #0
8002792: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
8002794: 2300 movs r3, #0
8002796: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8002798: 2300 movs r3, #0
800279a: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
800279c: 687b ldr r3, [r7, #4]
800279e: 681b ldr r3, [r3, #0]
80027a0: f003 0301 and.w r3, r3, #1
80027a4: 2b00 cmp r3, #0
80027a6: d012 beq.n 80027ce <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80027a8: 4b69 ldr r3, [pc, #420] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027aa: 689b ldr r3, [r3, #8]
80027ac: 4a68 ldr r2, [pc, #416] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027ae: f423 0300 bic.w r3, r3, #8388608 @ 0x800000
80027b2: 6093 str r3, [r2, #8]
80027b4: 4b66 ldr r3, [pc, #408] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027b6: 689a ldr r2, [r3, #8]
80027b8: 687b ldr r3, [r7, #4]
80027ba: 6b5b ldr r3, [r3, #52] @ 0x34
80027bc: 4964 ldr r1, [pc, #400] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027be: 4313 orrs r3, r2
80027c0: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
80027c2: 687b ldr r3, [r7, #4]
80027c4: 6b5b ldr r3, [r3, #52] @ 0x34
80027c6: 2b00 cmp r3, #0
80027c8: d101 bne.n 80027ce <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
80027ca: 2301 movs r3, #1
80027cc: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
80027ce: 687b ldr r3, [r7, #4]
80027d0: 681b ldr r3, [r3, #0]
80027d2: f403 2300 and.w r3, r3, #524288 @ 0x80000
80027d6: 2b00 cmp r3, #0
80027d8: d017 beq.n 800280a <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80027da: 4b5d ldr r3, [pc, #372] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027dc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
80027e0: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80027e4: 687b ldr r3, [r7, #4]
80027e6: 6bdb ldr r3, [r3, #60] @ 0x3c
80027e8: 4959 ldr r1, [pc, #356] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80027ea: 4313 orrs r3, r2
80027ec: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
80027f0: 687b ldr r3, [r7, #4]
80027f2: 6bdb ldr r3, [r3, #60] @ 0x3c
80027f4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80027f8: d101 bne.n 80027fe <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
80027fa: 2301 movs r3, #1
80027fc: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
80027fe: 687b ldr r3, [r7, #4]
8002800: 6bdb ldr r3, [r3, #60] @ 0x3c
8002802: 2b00 cmp r3, #0
8002804: d101 bne.n 800280a <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
8002806: 2301 movs r3, #1
8002808: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
800280a: 687b ldr r3, [r7, #4]
800280c: 681b ldr r3, [r3, #0]
800280e: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8002812: 2b00 cmp r3, #0
8002814: d017 beq.n 8002846 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8002816: 4b4e ldr r3, [pc, #312] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002818: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800281c: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8002820: 687b ldr r3, [r7, #4]
8002822: 6c1b ldr r3, [r3, #64] @ 0x40
8002824: 494a ldr r1, [pc, #296] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002826: 4313 orrs r3, r2
8002828: f8c1 308c str.w r3, [r1, #140] @ 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
800282c: 687b ldr r3, [r7, #4]
800282e: 6c1b ldr r3, [r3, #64] @ 0x40
8002830: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002834: d101 bne.n 800283a <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
8002836: 2301 movs r3, #1
8002838: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
800283a: 687b ldr r3, [r7, #4]
800283c: 6c1b ldr r3, [r3, #64] @ 0x40
800283e: 2b00 cmp r3, #0
8002840: d101 bne.n 8002846 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
8002842: 2301 movs r3, #1
8002844: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8002846: 687b ldr r3, [r7, #4]
8002848: 681b ldr r3, [r3, #0]
800284a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
800284e: 2b00 cmp r3, #0
8002850: d001 beq.n 8002856 <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
8002852: 2301 movs r3, #1
8002854: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002856: 687b ldr r3, [r7, #4]
8002858: 681b ldr r3, [r3, #0]
800285a: f003 0320 and.w r3, r3, #32
800285e: 2b00 cmp r3, #0
8002860: f000 808b beq.w 800297a <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002864: 4b3a ldr r3, [pc, #232] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002866: 6c1b ldr r3, [r3, #64] @ 0x40
8002868: 4a39 ldr r2, [pc, #228] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800286a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800286e: 6413 str r3, [r2, #64] @ 0x40
8002870: 4b37 ldr r3, [pc, #220] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002872: 6c1b ldr r3, [r3, #64] @ 0x40
8002874: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002878: 60bb str r3, [r7, #8]
800287a: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
800287c: 4b35 ldr r3, [pc, #212] @ (8002954 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
800287e: 681b ldr r3, [r3, #0]
8002880: 4a34 ldr r2, [pc, #208] @ (8002954 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8002882: f443 7380 orr.w r3, r3, #256 @ 0x100
8002886: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002888: f7fe fac8 bl 8000e1c <HAL_GetTick>
800288c: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
800288e: e008 b.n 80028a2 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002890: f7fe fac4 bl 8000e1c <HAL_GetTick>
8002894: 4602 mov r2, r0
8002896: 697b ldr r3, [r7, #20]
8002898: 1ad3 subs r3, r2, r3
800289a: 2b64 cmp r3, #100 @ 0x64
800289c: d901 bls.n 80028a2 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
800289e: 2303 movs r3, #3
80028a0: e38f b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80028a2: 4b2c ldr r3, [pc, #176] @ (8002954 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80028a4: 681b ldr r3, [r3, #0]
80028a6: f403 7380 and.w r3, r3, #256 @ 0x100
80028aa: 2b00 cmp r3, #0
80028ac: d0f0 beq.n 8002890 <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
80028ae: 4b28 ldr r3, [pc, #160] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028b0: 6f1b ldr r3, [r3, #112] @ 0x70
80028b2: f403 7340 and.w r3, r3, #768 @ 0x300
80028b6: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80028b8: 693b ldr r3, [r7, #16]
80028ba: 2b00 cmp r3, #0
80028bc: d035 beq.n 800292a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
80028be: 687b ldr r3, [r7, #4]
80028c0: 6b1b ldr r3, [r3, #48] @ 0x30
80028c2: f403 7340 and.w r3, r3, #768 @ 0x300
80028c6: 693a ldr r2, [r7, #16]
80028c8: 429a cmp r2, r3
80028ca: d02e beq.n 800292a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80028cc: 4b20 ldr r3, [pc, #128] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028ce: 6f1b ldr r3, [r3, #112] @ 0x70
80028d0: f423 7340 bic.w r3, r3, #768 @ 0x300
80028d4: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80028d6: 4b1e ldr r3, [pc, #120] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028d8: 6f1b ldr r3, [r3, #112] @ 0x70
80028da: 4a1d ldr r2, [pc, #116] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80028e0: 6713 str r3, [r2, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
80028e2: 4b1b ldr r3, [pc, #108] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028e4: 6f1b ldr r3, [r3, #112] @ 0x70
80028e6: 4a1a ldr r2, [pc, #104] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028e8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80028ec: 6713 str r3, [r2, #112] @ 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
80028ee: 4a18 ldr r2, [pc, #96] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028f0: 693b ldr r3, [r7, #16]
80028f2: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
80028f4: 4b16 ldr r3, [pc, #88] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80028f6: 6f1b ldr r3, [r3, #112] @ 0x70
80028f8: f003 0301 and.w r3, r3, #1
80028fc: 2b01 cmp r3, #1
80028fe: d114 bne.n 800292a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002900: f7fe fa8c bl 8000e1c <HAL_GetTick>
8002904: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002906: e00a b.n 800291e <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002908: f7fe fa88 bl 8000e1c <HAL_GetTick>
800290c: 4602 mov r2, r0
800290e: 697b ldr r3, [r7, #20]
8002910: 1ad3 subs r3, r2, r3
8002912: f241 3288 movw r2, #5000 @ 0x1388
8002916: 4293 cmp r3, r2
8002918: d901 bls.n 800291e <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
800291a: 2303 movs r3, #3
800291c: e351 b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800291e: 4b0c ldr r3, [pc, #48] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002920: 6f1b ldr r3, [r3, #112] @ 0x70
8002922: f003 0302 and.w r3, r3, #2
8002926: 2b00 cmp r3, #0
8002928: d0ee beq.n 8002908 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800292a: 687b ldr r3, [r7, #4]
800292c: 6b1b ldr r3, [r3, #48] @ 0x30
800292e: f403 7340 and.w r3, r3, #768 @ 0x300
8002932: f5b3 7f40 cmp.w r3, #768 @ 0x300
8002936: d111 bne.n 800295c <HAL_RCCEx_PeriphCLKConfig+0x1dc>
8002938: 4b05 ldr r3, [pc, #20] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800293a: 689b ldr r3, [r3, #8]
800293c: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
8002940: 687b ldr r3, [r7, #4]
8002942: 6b19 ldr r1, [r3, #48] @ 0x30
8002944: 4b04 ldr r3, [pc, #16] @ (8002958 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
8002946: 400b ands r3, r1
8002948: 4901 ldr r1, [pc, #4] @ (8002950 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800294a: 4313 orrs r3, r2
800294c: 608b str r3, [r1, #8]
800294e: e00b b.n 8002968 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
8002950: 40023800 .word 0x40023800
8002954: 40007000 .word 0x40007000
8002958: 0ffffcff .word 0x0ffffcff
800295c: 4bac ldr r3, [pc, #688] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
800295e: 689b ldr r3, [r3, #8]
8002960: 4aab ldr r2, [pc, #684] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002962: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
8002966: 6093 str r3, [r2, #8]
8002968: 4ba9 ldr r3, [pc, #676] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
800296a: 6f1a ldr r2, [r3, #112] @ 0x70
800296c: 687b ldr r3, [r7, #4]
800296e: 6b1b ldr r3, [r3, #48] @ 0x30
8002970: f3c3 030b ubfx r3, r3, #0, #12
8002974: 49a6 ldr r1, [pc, #664] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002976: 4313 orrs r3, r2
8002978: 670b str r3, [r1, #112] @ 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
800297a: 687b ldr r3, [r7, #4]
800297c: 681b ldr r3, [r3, #0]
800297e: f003 0310 and.w r3, r3, #16
8002982: 2b00 cmp r3, #0
8002984: d010 beq.n 80029a8 <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8002986: 4ba2 ldr r3, [pc, #648] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002988: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800298c: 4aa0 ldr r2, [pc, #640] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
800298e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8002992: f8c2 308c str.w r3, [r2, #140] @ 0x8c
8002996: 4b9e ldr r3, [pc, #632] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002998: f8d3 208c ldr.w r2, [r3, #140] @ 0x8c
800299c: 687b ldr r3, [r7, #4]
800299e: 6b9b ldr r3, [r3, #56] @ 0x38
80029a0: 499b ldr r1, [pc, #620] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029a2: 4313 orrs r3, r2
80029a4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80029a8: 687b ldr r3, [r7, #4]
80029aa: 681b ldr r3, [r3, #0]
80029ac: f403 4380 and.w r3, r3, #16384 @ 0x4000
80029b0: 2b00 cmp r3, #0
80029b2: d00a beq.n 80029ca <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80029b4: 4b96 ldr r3, [pc, #600] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029b6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80029ba: f423 3240 bic.w r2, r3, #196608 @ 0x30000
80029be: 687b ldr r3, [r7, #4]
80029c0: 6e5b ldr r3, [r3, #100] @ 0x64
80029c2: 4993 ldr r1, [pc, #588] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029c4: 4313 orrs r3, r2
80029c6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80029ca: 687b ldr r3, [r7, #4]
80029cc: 681b ldr r3, [r3, #0]
80029ce: f403 4300 and.w r3, r3, #32768 @ 0x8000
80029d2: 2b00 cmp r3, #0
80029d4: d00a beq.n 80029ec <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80029d6: 4b8e ldr r3, [pc, #568] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029d8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80029dc: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
80029e0: 687b ldr r3, [r7, #4]
80029e2: 6e9b ldr r3, [r3, #104] @ 0x68
80029e4: 498a ldr r1, [pc, #552] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029e6: 4313 orrs r3, r2
80029e8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
80029ec: 687b ldr r3, [r7, #4]
80029ee: 681b ldr r3, [r3, #0]
80029f0: f403 3380 and.w r3, r3, #65536 @ 0x10000
80029f4: 2b00 cmp r3, #0
80029f6: d00a beq.n 8002a0e <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
80029f8: 4b85 ldr r3, [pc, #532] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
80029fa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80029fe: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8002a02: 687b ldr r3, [r7, #4]
8002a04: 6edb ldr r3, [r3, #108] @ 0x6c
8002a06: 4982 ldr r1, [pc, #520] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a08: 4313 orrs r3, r2
8002a0a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8002a0e: 687b ldr r3, [r7, #4]
8002a10: 681b ldr r3, [r3, #0]
8002a12: f403 3300 and.w r3, r3, #131072 @ 0x20000
8002a16: 2b00 cmp r3, #0
8002a18: d00a beq.n 8002a30 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8002a1a: 4b7d ldr r3, [pc, #500] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a1c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002a20: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
8002a24: 687b ldr r3, [r7, #4]
8002a26: 6f1b ldr r3, [r3, #112] @ 0x70
8002a28: 4979 ldr r1, [pc, #484] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a2a: 4313 orrs r3, r2
8002a2c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8002a30: 687b ldr r3, [r7, #4]
8002a32: 681b ldr r3, [r3, #0]
8002a34: f003 0340 and.w r3, r3, #64 @ 0x40
8002a38: 2b00 cmp r3, #0
8002a3a: d00a beq.n 8002a52 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8002a3c: 4b74 ldr r3, [pc, #464] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a3e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002a42: f023 0203 bic.w r2, r3, #3
8002a46: 687b ldr r3, [r7, #4]
8002a48: 6c5b ldr r3, [r3, #68] @ 0x44
8002a4a: 4971 ldr r1, [pc, #452] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a4c: 4313 orrs r3, r2
8002a4e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8002a52: 687b ldr r3, [r7, #4]
8002a54: 681b ldr r3, [r3, #0]
8002a56: f003 0380 and.w r3, r3, #128 @ 0x80
8002a5a: 2b00 cmp r3, #0
8002a5c: d00a beq.n 8002a74 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8002a5e: 4b6c ldr r3, [pc, #432] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a60: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002a64: f023 020c bic.w r2, r3, #12
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 6c9b ldr r3, [r3, #72] @ 0x48
8002a6c: 4968 ldr r1, [pc, #416] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a6e: 4313 orrs r3, r2
8002a70: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8002a74: 687b ldr r3, [r7, #4]
8002a76: 681b ldr r3, [r3, #0]
8002a78: f403 7380 and.w r3, r3, #256 @ 0x100
8002a7c: 2b00 cmp r3, #0
8002a7e: d00a beq.n 8002a96 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8002a80: 4b63 ldr r3, [pc, #396] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a82: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002a86: f023 0230 bic.w r2, r3, #48 @ 0x30
8002a8a: 687b ldr r3, [r7, #4]
8002a8c: 6cdb ldr r3, [r3, #76] @ 0x4c
8002a8e: 4960 ldr r1, [pc, #384] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002a90: 4313 orrs r3, r2
8002a92: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8002a96: 687b ldr r3, [r7, #4]
8002a98: 681b ldr r3, [r3, #0]
8002a9a: f403 7300 and.w r3, r3, #512 @ 0x200
8002a9e: 2b00 cmp r3, #0
8002aa0: d00a beq.n 8002ab8 <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8002aa2: 4b5b ldr r3, [pc, #364] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002aa4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002aa8: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8002aac: 687b ldr r3, [r7, #4]
8002aae: 6d1b ldr r3, [r3, #80] @ 0x50
8002ab0: 4957 ldr r1, [pc, #348] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002ab2: 4313 orrs r3, r2
8002ab4: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8002ab8: 687b ldr r3, [r7, #4]
8002aba: 681b ldr r3, [r3, #0]
8002abc: f403 6380 and.w r3, r3, #1024 @ 0x400
8002ac0: 2b00 cmp r3, #0
8002ac2: d00a beq.n 8002ada <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8002ac4: 4b52 ldr r3, [pc, #328] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002ac6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002aca: f423 7240 bic.w r2, r3, #768 @ 0x300
8002ace: 687b ldr r3, [r7, #4]
8002ad0: 6d5b ldr r3, [r3, #84] @ 0x54
8002ad2: 494f ldr r1, [pc, #316] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002ad4: 4313 orrs r3, r2
8002ad6: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
8002ada: 687b ldr r3, [r7, #4]
8002adc: 681b ldr r3, [r3, #0]
8002ade: f403 6300 and.w r3, r3, #2048 @ 0x800
8002ae2: 2b00 cmp r3, #0
8002ae4: d00a beq.n 8002afc <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8002ae6: 4b4a ldr r3, [pc, #296] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002ae8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002aec: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8002af0: 687b ldr r3, [r7, #4]
8002af2: 6d9b ldr r3, [r3, #88] @ 0x58
8002af4: 4946 ldr r1, [pc, #280] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002af6: 4313 orrs r3, r2
8002af8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8002afc: 687b ldr r3, [r7, #4]
8002afe: 681b ldr r3, [r3, #0]
8002b00: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002b04: 2b00 cmp r3, #0
8002b06: d00a beq.n 8002b1e <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8002b08: 4b41 ldr r3, [pc, #260] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b0a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b0e: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8002b12: 687b ldr r3, [r7, #4]
8002b14: 6ddb ldr r3, [r3, #92] @ 0x5c
8002b16: 493e ldr r1, [pc, #248] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b18: 4313 orrs r3, r2
8002b1a: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
8002b1e: 687b ldr r3, [r7, #4]
8002b20: 681b ldr r3, [r3, #0]
8002b22: f403 5300 and.w r3, r3, #8192 @ 0x2000
8002b26: 2b00 cmp r3, #0
8002b28: d00a beq.n 8002b40 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8002b2a: 4b39 ldr r3, [pc, #228] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b2c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b30: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8002b34: 687b ldr r3, [r7, #4]
8002b36: 6e1b ldr r3, [r3, #96] @ 0x60
8002b38: 4935 ldr r1, [pc, #212] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b3a: 4313 orrs r3, r2
8002b3c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8002b40: 687b ldr r3, [r7, #4]
8002b42: 681b ldr r3, [r3, #0]
8002b44: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002b48: 2b00 cmp r3, #0
8002b4a: d00a beq.n 8002b62 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8002b4c: 4b30 ldr r3, [pc, #192] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b4e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b52: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
8002b56: 687b ldr r3, [r7, #4]
8002b58: 6f9b ldr r3, [r3, #120] @ 0x78
8002b5a: 492d ldr r1, [pc, #180] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b5c: 4313 orrs r3, r2
8002b5e: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
8002b62: 687b ldr r3, [r7, #4]
8002b64: 681b ldr r3, [r3, #0]
8002b66: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002b6a: 2b00 cmp r3, #0
8002b6c: d011 beq.n 8002b92 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
8002b6e: 4b28 ldr r3, [pc, #160] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b70: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002b74: f023 6200 bic.w r2, r3, #134217728 @ 0x8000000
8002b78: 687b ldr r3, [r7, #4]
8002b7a: 6fdb ldr r3, [r3, #124] @ 0x7c
8002b7c: 4924 ldr r1, [pc, #144] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002b7e: 4313 orrs r3, r2
8002b80: f8c1 3090 str.w r3, [r1, #144] @ 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
8002b84: 687b ldr r3, [r7, #4]
8002b86: 6fdb ldr r3, [r3, #124] @ 0x7c
8002b88: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8002b8c: d101 bne.n 8002b92 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
8002b8e: 2301 movs r3, #1
8002b90: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
8002b92: 687b ldr r3, [r7, #4]
8002b94: 681b ldr r3, [r3, #0]
8002b96: f003 0308 and.w r3, r3, #8
8002b9a: 2b00 cmp r3, #0
8002b9c: d001 beq.n 8002ba2 <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
8002b9e: 2301 movs r3, #1
8002ba0: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8002ba2: 687b ldr r3, [r7, #4]
8002ba4: 681b ldr r3, [r3, #0]
8002ba6: f403 2380 and.w r3, r3, #262144 @ 0x40000
8002baa: 2b00 cmp r3, #0
8002bac: d00a beq.n 8002bc4 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8002bae: 4b18 ldr r3, [pc, #96] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002bb0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002bb4: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8002bb8: 687b ldr r3, [r7, #4]
8002bba: 6f5b ldr r3, [r3, #116] @ 0x74
8002bbc: 4914 ldr r1, [pc, #80] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002bbe: 4313 orrs r3, r2
8002bc0: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
8002bc4: 687b ldr r3, [r7, #4]
8002bc6: 681b ldr r3, [r3, #0]
8002bc8: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002bcc: 2b00 cmp r3, #0
8002bce: d00b beq.n 8002be8 <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8002bd0: 4b0f ldr r3, [pc, #60] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002bd2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002bd6: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8002bda: 687b ldr r3, [r7, #4]
8002bdc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8002be0: 490b ldr r1, [pc, #44] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002be2: 4313 orrs r3, r2
8002be4: f8c1 3090 str.w r3, [r1, #144] @ 0x90
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
8002be8: 687b ldr r3, [r7, #4]
8002bea: 681b ldr r3, [r3, #0]
8002bec: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8002bf0: 2b00 cmp r3, #0
8002bf2: d00f beq.n 8002c14 <HAL_RCCEx_PeriphCLKConfig+0x494>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
8002bf4: 4b06 ldr r3, [pc, #24] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002bf6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8002bfa: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
8002bfe: 687b ldr r3, [r7, #4]
8002c00: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002c04: 4902 ldr r1, [pc, #8] @ (8002c10 <HAL_RCCEx_PeriphCLKConfig+0x490>)
8002c06: 4313 orrs r3, r2
8002c08: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8002c0c: e002 b.n 8002c14 <HAL_RCCEx_PeriphCLKConfig+0x494>
8002c0e: bf00 nop
8002c10: 40023800 .word 0x40023800
}
/*------------------------------------- DFSDM1 Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
8002c14: 687b ldr r3, [r7, #4]
8002c16: 681b ldr r3, [r3, #0]
8002c18: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8002c1c: 2b00 cmp r3, #0
8002c1e: d00b beq.n 8002c38 <HAL_RCCEx_PeriphCLKConfig+0x4b8>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
8002c20: 4b8a ldr r3, [pc, #552] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c22: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002c26: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
8002c2a: 687b ldr r3, [r7, #4]
8002c2c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002c30: 4986 ldr r1, [pc, #536] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c32: 4313 orrs r3, r2
8002c34: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 681b ldr r3, [r3, #0]
8002c3c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8002c40: 2b00 cmp r3, #0
8002c42: d00b beq.n 8002c5c <HAL_RCCEx_PeriphCLKConfig+0x4dc>
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
/* Configure the DFSDM interface clock source */
__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
8002c44: 4b81 ldr r3, [pc, #516] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c46: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002c4a: f023 6280 bic.w r2, r3, #67108864 @ 0x4000000
8002c4e: 687b ldr r3, [r7, #4]
8002c50: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002c54: 497d ldr r1, [pc, #500] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c56: 4313 orrs r3, r2
8002c58: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8002c5c: 69fb ldr r3, [r7, #28]
8002c5e: 2b01 cmp r3, #1
8002c60: d006 beq.n 8002c70 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
8002c62: 687b ldr r3, [r7, #4]
8002c64: 681b ldr r3, [r3, #0]
8002c66: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002c6a: 2b00 cmp r3, #0
8002c6c: f000 80d6 beq.w 8002e1c <HAL_RCCEx_PeriphCLKConfig+0x69c>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8002c70: 4b76 ldr r3, [pc, #472] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c72: 681b ldr r3, [r3, #0]
8002c74: 4a75 ldr r2, [pc, #468] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c76: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8002c7a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002c7c: f7fe f8ce bl 8000e1c <HAL_GetTick>
8002c80: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002c82: e008 b.n 8002c96 <HAL_RCCEx_PeriphCLKConfig+0x516>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8002c84: f7fe f8ca bl 8000e1c <HAL_GetTick>
8002c88: 4602 mov r2, r0
8002c8a: 697b ldr r3, [r7, #20]
8002c8c: 1ad3 subs r3, r2, r3
8002c8e: 2b64 cmp r3, #100 @ 0x64
8002c90: d901 bls.n 8002c96 <HAL_RCCEx_PeriphCLKConfig+0x516>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002c92: 2303 movs r3, #3
8002c94: e195 b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002c96: 4b6d ldr r3, [pc, #436] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002c98: 681b ldr r3, [r3, #0]
8002c9a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8002c9e: 2b00 cmp r3, #0
8002ca0: d1f0 bne.n 8002c84 <HAL_RCCEx_PeriphCLKConfig+0x504>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8002ca2: 687b ldr r3, [r7, #4]
8002ca4: 681b ldr r3, [r3, #0]
8002ca6: f003 0301 and.w r3, r3, #1
8002caa: 2b00 cmp r3, #0
8002cac: d021 beq.n 8002cf2 <HAL_RCCEx_PeriphCLKConfig+0x572>
8002cae: 687b ldr r3, [r7, #4]
8002cb0: 6b5b ldr r3, [r3, #52] @ 0x34
8002cb2: 2b00 cmp r3, #0
8002cb4: d11d bne.n 8002cf2 <HAL_RCCEx_PeriphCLKConfig+0x572>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8002cb6: 4b65 ldr r3, [pc, #404] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002cb8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002cbc: 0c1b lsrs r3, r3, #16
8002cbe: f003 0303 and.w r3, r3, #3
8002cc2: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8002cc4: 4b61 ldr r3, [pc, #388] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002cc6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002cca: 0e1b lsrs r3, r3, #24
8002ccc: f003 030f and.w r3, r3, #15
8002cd0: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
8002cd2: 687b ldr r3, [r7, #4]
8002cd4: 685b ldr r3, [r3, #4]
8002cd6: 019a lsls r2, r3, #6
8002cd8: 693b ldr r3, [r7, #16]
8002cda: 041b lsls r3, r3, #16
8002cdc: 431a orrs r2, r3
8002cde: 68fb ldr r3, [r7, #12]
8002ce0: 061b lsls r3, r3, #24
8002ce2: 431a orrs r2, r3
8002ce4: 687b ldr r3, [r7, #4]
8002ce6: 689b ldr r3, [r3, #8]
8002ce8: 071b lsls r3, r3, #28
8002cea: 4958 ldr r1, [pc, #352] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002cec: 4313 orrs r3, r2
8002cee: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
8002cf2: 687b ldr r3, [r7, #4]
8002cf4: 681b ldr r3, [r3, #0]
8002cf6: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002cfa: 2b00 cmp r3, #0
8002cfc: d004 beq.n 8002d08 <HAL_RCCEx_PeriphCLKConfig+0x588>
8002cfe: 687b ldr r3, [r7, #4]
8002d00: 6bdb ldr r3, [r3, #60] @ 0x3c
8002d02: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002d06: d00a beq.n 8002d1e <HAL_RCCEx_PeriphCLKConfig+0x59e>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 681b ldr r3, [r3, #0]
8002d0c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
8002d10: 2b00 cmp r3, #0
8002d12: d02e beq.n 8002d72 <HAL_RCCEx_PeriphCLKConfig+0x5f2>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
8002d14: 687b ldr r3, [r7, #4]
8002d16: 6c1b ldr r3, [r3, #64] @ 0x40
8002d18: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8002d1c: d129 bne.n 8002d72 <HAL_RCCEx_PeriphCLKConfig+0x5f2>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8002d1e: 4b4b ldr r3, [pc, #300] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d20: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002d24: 0c1b lsrs r3, r3, #16
8002d26: f003 0303 and.w r3, r3, #3
8002d2a: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8002d2c: 4b47 ldr r3, [pc, #284] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d2e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002d32: 0f1b lsrs r3, r3, #28
8002d34: f003 0307 and.w r3, r3, #7
8002d38: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
8002d3a: 687b ldr r3, [r7, #4]
8002d3c: 685b ldr r3, [r3, #4]
8002d3e: 019a lsls r2, r3, #6
8002d40: 693b ldr r3, [r7, #16]
8002d42: 041b lsls r3, r3, #16
8002d44: 431a orrs r2, r3
8002d46: 687b ldr r3, [r7, #4]
8002d48: 68db ldr r3, [r3, #12]
8002d4a: 061b lsls r3, r3, #24
8002d4c: 431a orrs r2, r3
8002d4e: 68fb ldr r3, [r7, #12]
8002d50: 071b lsls r3, r3, #28
8002d52: 493e ldr r1, [pc, #248] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d54: 4313 orrs r3, r2
8002d56: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8002d5a: 4b3c ldr r3, [pc, #240] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d5c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002d60: f023 021f bic.w r2, r3, #31
8002d64: 687b ldr r3, [r7, #4]
8002d66: 6a5b ldr r3, [r3, #36] @ 0x24
8002d68: 3b01 subs r3, #1
8002d6a: 4938 ldr r1, [pc, #224] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d6c: 4313 orrs r3, r2
8002d6e: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8002d72: 687b ldr r3, [r7, #4]
8002d74: 681b ldr r3, [r3, #0]
8002d76: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8002d7a: 2b00 cmp r3, #0
8002d7c: d01d beq.n 8002dba <HAL_RCCEx_PeriphCLKConfig+0x63a>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8002d7e: 4b33 ldr r3, [pc, #204] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d80: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002d84: 0e1b lsrs r3, r3, #24
8002d86: f003 030f and.w r3, r3, #15
8002d8a: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8002d8c: 4b2f ldr r3, [pc, #188] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002d8e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8002d92: 0f1b lsrs r3, r3, #28
8002d94: f003 0307 and.w r3, r3, #7
8002d98: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
8002d9a: 687b ldr r3, [r7, #4]
8002d9c: 685b ldr r3, [r3, #4]
8002d9e: 019a lsls r2, r3, #6
8002da0: 687b ldr r3, [r7, #4]
8002da2: 691b ldr r3, [r3, #16]
8002da4: 041b lsls r3, r3, #16
8002da6: 431a orrs r2, r3
8002da8: 693b ldr r3, [r7, #16]
8002daa: 061b lsls r3, r3, #24
8002dac: 431a orrs r2, r3
8002dae: 68fb ldr r3, [r7, #12]
8002db0: 071b lsls r3, r3, #28
8002db2: 4926 ldr r1, [pc, #152] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002db4: 4313 orrs r3, r2
8002db6: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8002dba: 687b ldr r3, [r7, #4]
8002dbc: 681b ldr r3, [r3, #0]
8002dbe: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002dc2: 2b00 cmp r3, #0
8002dc4: d011 beq.n 8002dea <HAL_RCCEx_PeriphCLKConfig+0x66a>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8002dc6: 687b ldr r3, [r7, #4]
8002dc8: 685b ldr r3, [r3, #4]
8002dca: 019a lsls r2, r3, #6
8002dcc: 687b ldr r3, [r7, #4]
8002dce: 691b ldr r3, [r3, #16]
8002dd0: 041b lsls r3, r3, #16
8002dd2: 431a orrs r2, r3
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 68db ldr r3, [r3, #12]
8002dd8: 061b lsls r3, r3, #24
8002dda: 431a orrs r2, r3
8002ddc: 687b ldr r3, [r7, #4]
8002dde: 689b ldr r3, [r3, #8]
8002de0: 071b lsls r3, r3, #28
8002de2: 491a ldr r1, [pc, #104] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002de4: 4313 orrs r3, r2
8002de6: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8002dea: 4b18 ldr r3, [pc, #96] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002dec: 681b ldr r3, [r3, #0]
8002dee: 4a17 ldr r2, [pc, #92] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002df0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8002df4: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002df6: f7fe f811 bl 8000e1c <HAL_GetTick>
8002dfa: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8002dfc: e008 b.n 8002e10 <HAL_RCCEx_PeriphCLKConfig+0x690>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8002dfe: f7fe f80d bl 8000e1c <HAL_GetTick>
8002e02: 4602 mov r2, r0
8002e04: 697b ldr r3, [r7, #20]
8002e06: 1ad3 subs r3, r2, r3
8002e08: 2b64 cmp r3, #100 @ 0x64
8002e0a: d901 bls.n 8002e10 <HAL_RCCEx_PeriphCLKConfig+0x690>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002e0c: 2303 movs r3, #3
8002e0e: e0d8 b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8002e10: 4b0e ldr r3, [pc, #56] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002e12: 681b ldr r3, [r3, #0]
8002e14: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8002e18: 2b00 cmp r3, #0
8002e1a: d0f0 beq.n 8002dfe <HAL_RCCEx_PeriphCLKConfig+0x67e>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
8002e1c: 69bb ldr r3, [r7, #24]
8002e1e: 2b01 cmp r3, #1
8002e20: f040 80ce bne.w 8002fc0 <HAL_RCCEx_PeriphCLKConfig+0x840>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
8002e24: 4b09 ldr r3, [pc, #36] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002e26: 681b ldr r3, [r3, #0]
8002e28: 4a08 ldr r2, [pc, #32] @ (8002e4c <HAL_RCCEx_PeriphCLKConfig+0x6cc>)
8002e2a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002e2e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e30: f7fd fff4 bl 8000e1c <HAL_GetTick>
8002e34: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8002e36: e00b b.n 8002e50 <HAL_RCCEx_PeriphCLKConfig+0x6d0>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8002e38: f7fd fff0 bl 8000e1c <HAL_GetTick>
8002e3c: 4602 mov r2, r0
8002e3e: 697b ldr r3, [r7, #20]
8002e40: 1ad3 subs r3, r2, r3
8002e42: 2b64 cmp r3, #100 @ 0x64
8002e44: d904 bls.n 8002e50 <HAL_RCCEx_PeriphCLKConfig+0x6d0>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002e46: 2303 movs r3, #3
8002e48: e0bb b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
8002e4a: bf00 nop
8002e4c: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8002e50: 4b5e ldr r3, [pc, #376] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002e52: 681b ldr r3, [r3, #0]
8002e54: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002e58: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8002e5c: d0ec beq.n 8002e38 <HAL_RCCEx_PeriphCLKConfig+0x6b8>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8002e5e: 687b ldr r3, [r7, #4]
8002e60: 681b ldr r3, [r3, #0]
8002e62: f403 2300 and.w r3, r3, #524288 @ 0x80000
8002e66: 2b00 cmp r3, #0
8002e68: d003 beq.n 8002e72 <HAL_RCCEx_PeriphCLKConfig+0x6f2>
8002e6a: 687b ldr r3, [r7, #4]
8002e6c: 6bdb ldr r3, [r3, #60] @ 0x3c
8002e6e: 2b00 cmp r3, #0
8002e70: d009 beq.n 8002e86 <HAL_RCCEx_PeriphCLKConfig+0x706>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8002e72: 687b ldr r3, [r7, #4]
8002e74: 681b ldr r3, [r3, #0]
8002e76: f403 1380 and.w r3, r3, #1048576 @ 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8002e7a: 2b00 cmp r3, #0
8002e7c: d02e beq.n 8002edc <HAL_RCCEx_PeriphCLKConfig+0x75c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8002e7e: 687b ldr r3, [r7, #4]
8002e80: 6c1b ldr r3, [r3, #64] @ 0x40
8002e82: 2b00 cmp r3, #0
8002e84: d12a bne.n 8002edc <HAL_RCCEx_PeriphCLKConfig+0x75c>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8002e86: 4b51 ldr r3, [pc, #324] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002e88: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002e8c: 0c1b lsrs r3, r3, #16
8002e8e: f003 0303 and.w r3, r3, #3
8002e92: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8002e94: 4b4d ldr r3, [pc, #308] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002e96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002e9a: 0f1b lsrs r3, r3, #28
8002e9c: f003 0307 and.w r3, r3, #7
8002ea0: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
8002ea2: 687b ldr r3, [r7, #4]
8002ea4: 695b ldr r3, [r3, #20]
8002ea6: 019a lsls r2, r3, #6
8002ea8: 693b ldr r3, [r7, #16]
8002eaa: 041b lsls r3, r3, #16
8002eac: 431a orrs r2, r3
8002eae: 687b ldr r3, [r7, #4]
8002eb0: 699b ldr r3, [r3, #24]
8002eb2: 061b lsls r3, r3, #24
8002eb4: 431a orrs r2, r3
8002eb6: 68fb ldr r3, [r7, #12]
8002eb8: 071b lsls r3, r3, #28
8002eba: 4944 ldr r1, [pc, #272] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002ebc: 4313 orrs r3, r2
8002ebe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
8002ec2: 4b42 ldr r3, [pc, #264] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002ec4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002ec8: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8002ecc: 687b ldr r3, [r7, #4]
8002ece: 6a9b ldr r3, [r3, #40] @ 0x28
8002ed0: 3b01 subs r3, #1
8002ed2: 021b lsls r3, r3, #8
8002ed4: 493d ldr r1, [pc, #244] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002ed6: 4313 orrs r3, r2
8002ed8: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8002edc: 687b ldr r3, [r7, #4]
8002ede: 681b ldr r3, [r3, #0]
8002ee0: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002ee4: 2b00 cmp r3, #0
8002ee6: d022 beq.n 8002f2e <HAL_RCCEx_PeriphCLKConfig+0x7ae>
8002ee8: 687b ldr r3, [r7, #4]
8002eea: 6fdb ldr r3, [r3, #124] @ 0x7c
8002eec: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
8002ef0: d11d bne.n 8002f2e <HAL_RCCEx_PeriphCLKConfig+0x7ae>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8002ef2: 4b36 ldr r3, [pc, #216] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002ef4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002ef8: 0e1b lsrs r3, r3, #24
8002efa: f003 030f and.w r3, r3, #15
8002efe: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8002f00: 4b32 ldr r3, [pc, #200] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f02: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002f06: 0f1b lsrs r3, r3, #28
8002f08: f003 0307 and.w r3, r3, #7
8002f0c: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
8002f0e: 687b ldr r3, [r7, #4]
8002f10: 695b ldr r3, [r3, #20]
8002f12: 019a lsls r2, r3, #6
8002f14: 687b ldr r3, [r7, #4]
8002f16: 6a1b ldr r3, [r3, #32]
8002f18: 041b lsls r3, r3, #16
8002f1a: 431a orrs r2, r3
8002f1c: 693b ldr r3, [r7, #16]
8002f1e: 061b lsls r3, r3, #24
8002f20: 431a orrs r2, r3
8002f22: 68fb ldr r3, [r7, #12]
8002f24: 071b lsls r3, r3, #28
8002f26: 4929 ldr r1, [pc, #164] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f28: 4313 orrs r3, r2
8002f2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
8002f2e: 687b ldr r3, [r7, #4]
8002f30: 681b ldr r3, [r3, #0]
8002f32: f003 0308 and.w r3, r3, #8
8002f36: 2b00 cmp r3, #0
8002f38: d028 beq.n 8002f8c <HAL_RCCEx_PeriphCLKConfig+0x80c>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8002f3a: 4b24 ldr r3, [pc, #144] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f3c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002f40: 0e1b lsrs r3, r3, #24
8002f42: f003 030f and.w r3, r3, #15
8002f46: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8002f48: 4b20 ldr r3, [pc, #128] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f4a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8002f4e: 0c1b lsrs r3, r3, #16
8002f50: f003 0303 and.w r3, r3, #3
8002f54: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
8002f56: 687b ldr r3, [r7, #4]
8002f58: 695b ldr r3, [r3, #20]
8002f5a: 019a lsls r2, r3, #6
8002f5c: 68fb ldr r3, [r7, #12]
8002f5e: 041b lsls r3, r3, #16
8002f60: 431a orrs r2, r3
8002f62: 693b ldr r3, [r7, #16]
8002f64: 061b lsls r3, r3, #24
8002f66: 431a orrs r2, r3
8002f68: 687b ldr r3, [r7, #4]
8002f6a: 69db ldr r3, [r3, #28]
8002f6c: 071b lsls r3, r3, #28
8002f6e: 4917 ldr r1, [pc, #92] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f70: 4313 orrs r3, r2
8002f72: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
8002f76: 4b15 ldr r3, [pc, #84] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f78: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8002f7c: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8002f80: 687b ldr r3, [r7, #4]
8002f82: 6adb ldr r3, [r3, #44] @ 0x2c
8002f84: 4911 ldr r1, [pc, #68] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f86: 4313 orrs r3, r2
8002f88: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8002f8c: 4b0f ldr r3, [pc, #60] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f8e: 681b ldr r3, [r3, #0]
8002f90: 4a0e ldr r2, [pc, #56] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002f92: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002f96: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002f98: f7fd ff40 bl 8000e1c <HAL_GetTick>
8002f9c: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002f9e: e008 b.n 8002fb2 <HAL_RCCEx_PeriphCLKConfig+0x832>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8002fa0: f7fd ff3c bl 8000e1c <HAL_GetTick>
8002fa4: 4602 mov r2, r0
8002fa6: 697b ldr r3, [r7, #20]
8002fa8: 1ad3 subs r3, r2, r3
8002faa: 2b64 cmp r3, #100 @ 0x64
8002fac: d901 bls.n 8002fb2 <HAL_RCCEx_PeriphCLKConfig+0x832>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002fae: 2303 movs r3, #3
8002fb0: e007 b.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x842>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8002fb2: 4b06 ldr r3, [pc, #24] @ (8002fcc <HAL_RCCEx_PeriphCLKConfig+0x84c>)
8002fb4: 681b ldr r3, [r3, #0]
8002fb6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8002fba: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8002fbe: d1ef bne.n 8002fa0 <HAL_RCCEx_PeriphCLKConfig+0x820>
}
}
}
return HAL_OK;
8002fc0: 2300 movs r3, #0
}
8002fc2: 4618 mov r0, r3
8002fc4: 3720 adds r7, #32
8002fc6: 46bd mov sp, r7
8002fc8: bd80 pop {r7, pc}
8002fca: bf00 nop
8002fcc: 40023800 .word 0x40023800
08002fd0 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002fd0: b580 push {r7, lr}
8002fd2: b082 sub sp, #8
8002fd4: af00 add r7, sp, #0
8002fd6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002fd8: 687b ldr r3, [r7, #4]
8002fda: 2b00 cmp r3, #0
8002fdc: d101 bne.n 8002fe2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8002fde: 2301 movs r3, #1
8002fe0: e040 b.n 8003064 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
8002fe2: 687b ldr r3, [r7, #4]
8002fe4: 6fdb ldr r3, [r3, #124] @ 0x7c
8002fe6: 2b00 cmp r3, #0
8002fe8: d106 bne.n 8002ff8 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8002fea: 687b ldr r3, [r7, #4]
8002fec: 2200 movs r2, #0
8002fee: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002ff2: 6878 ldr r0, [r7, #4]
8002ff4: f7fd fd7c bl 8000af0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8002ff8: 687b ldr r3, [r7, #4]
8002ffa: 2224 movs r2, #36 @ 0x24
8002ffc: 67da str r2, [r3, #124] @ 0x7c
__HAL_UART_DISABLE(huart);
8002ffe: 687b ldr r3, [r7, #4]
8003000: 681b ldr r3, [r3, #0]
8003002: 681a ldr r2, [r3, #0]
8003004: 687b ldr r3, [r7, #4]
8003006: 681b ldr r3, [r3, #0]
8003008: f022 0201 bic.w r2, r2, #1
800300c: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800300e: 687b ldr r3, [r7, #4]
8003010: 6a5b ldr r3, [r3, #36] @ 0x24
8003012: 2b00 cmp r3, #0
8003014: d002 beq.n 800301c <HAL_UART_Init+0x4c>
{
UART_AdvFeatureConfig(huart);
8003016: 6878 ldr r0, [r7, #4]
8003018: f000 fa8c bl 8003534 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
800301c: 6878 ldr r0, [r7, #4]
800301e: f000 f825 bl 800306c <UART_SetConfig>
8003022: 4603 mov r3, r0
8003024: 2b01 cmp r3, #1
8003026: d101 bne.n 800302c <HAL_UART_Init+0x5c>
{
return HAL_ERROR;
8003028: 2301 movs r3, #1
800302a: e01b b.n 8003064 <HAL_UART_Init+0x94>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800302c: 687b ldr r3, [r7, #4]
800302e: 681b ldr r3, [r3, #0]
8003030: 685a ldr r2, [r3, #4]
8003032: 687b ldr r3, [r7, #4]
8003034: 681b ldr r3, [r3, #0]
8003036: f422 4290 bic.w r2, r2, #18432 @ 0x4800
800303a: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800303c: 687b ldr r3, [r7, #4]
800303e: 681b ldr r3, [r3, #0]
8003040: 689a ldr r2, [r3, #8]
8003042: 687b ldr r3, [r7, #4]
8003044: 681b ldr r3, [r3, #0]
8003046: f022 022a bic.w r2, r2, #42 @ 0x2a
800304a: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800304c: 687b ldr r3, [r7, #4]
800304e: 681b ldr r3, [r3, #0]
8003050: 681a ldr r2, [r3, #0]
8003052: 687b ldr r3, [r7, #4]
8003054: 681b ldr r3, [r3, #0]
8003056: f042 0201 orr.w r2, r2, #1
800305a: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800305c: 6878 ldr r0, [r7, #4]
800305e: f000 fb0b bl 8003678 <UART_CheckIdleState>
8003062: 4603 mov r3, r0
}
8003064: 4618 mov r0, r3
8003066: 3708 adds r7, #8
8003068: 46bd mov sp, r7
800306a: bd80 pop {r7, pc}
0800306c <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
800306c: b580 push {r7, lr}
800306e: b088 sub sp, #32
8003070: af00 add r7, sp, #0
8003072: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8003074: 2300 movs r3, #0
8003076: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003078: 687b ldr r3, [r7, #4]
800307a: 689a ldr r2, [r3, #8]
800307c: 687b ldr r3, [r7, #4]
800307e: 691b ldr r3, [r3, #16]
8003080: 431a orrs r2, r3
8003082: 687b ldr r3, [r7, #4]
8003084: 695b ldr r3, [r3, #20]
8003086: 431a orrs r2, r3
8003088: 687b ldr r3, [r7, #4]
800308a: 69db ldr r3, [r3, #28]
800308c: 4313 orrs r3, r2
800308e: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8003090: 687b ldr r3, [r7, #4]
8003092: 681b ldr r3, [r3, #0]
8003094: 681a ldr r2, [r3, #0]
8003096: 4ba6 ldr r3, [pc, #664] @ (8003330 <UART_SetConfig+0x2c4>)
8003098: 4013 ands r3, r2
800309a: 687a ldr r2, [r7, #4]
800309c: 6812 ldr r2, [r2, #0]
800309e: 6979 ldr r1, [r7, #20]
80030a0: 430b orrs r3, r1
80030a2: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80030a4: 687b ldr r3, [r7, #4]
80030a6: 681b ldr r3, [r3, #0]
80030a8: 685b ldr r3, [r3, #4]
80030aa: f423 5140 bic.w r1, r3, #12288 @ 0x3000
80030ae: 687b ldr r3, [r7, #4]
80030b0: 68da ldr r2, [r3, #12]
80030b2: 687b ldr r3, [r7, #4]
80030b4: 681b ldr r3, [r3, #0]
80030b6: 430a orrs r2, r1
80030b8: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80030ba: 687b ldr r3, [r7, #4]
80030bc: 699b ldr r3, [r3, #24]
80030be: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
80030c0: 687b ldr r3, [r7, #4]
80030c2: 6a1b ldr r3, [r3, #32]
80030c4: 697a ldr r2, [r7, #20]
80030c6: 4313 orrs r3, r2
80030c8: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80030ca: 687b ldr r3, [r7, #4]
80030cc: 681b ldr r3, [r3, #0]
80030ce: 689b ldr r3, [r3, #8]
80030d0: f423 6130 bic.w r1, r3, #2816 @ 0xb00
80030d4: 687b ldr r3, [r7, #4]
80030d6: 681b ldr r3, [r3, #0]
80030d8: 697a ldr r2, [r7, #20]
80030da: 430a orrs r2, r1
80030dc: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
80030de: 687b ldr r3, [r7, #4]
80030e0: 681b ldr r3, [r3, #0]
80030e2: 4a94 ldr r2, [pc, #592] @ (8003334 <UART_SetConfig+0x2c8>)
80030e4: 4293 cmp r3, r2
80030e6: d120 bne.n 800312a <UART_SetConfig+0xbe>
80030e8: 4b93 ldr r3, [pc, #588] @ (8003338 <UART_SetConfig+0x2cc>)
80030ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80030ee: f003 0303 and.w r3, r3, #3
80030f2: 2b03 cmp r3, #3
80030f4: d816 bhi.n 8003124 <UART_SetConfig+0xb8>
80030f6: a201 add r2, pc, #4 @ (adr r2, 80030fc <UART_SetConfig+0x90>)
80030f8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80030fc: 0800310d .word 0x0800310d
8003100: 08003119 .word 0x08003119
8003104: 08003113 .word 0x08003113
8003108: 0800311f .word 0x0800311f
800310c: 2301 movs r3, #1
800310e: 77fb strb r3, [r7, #31]
8003110: e150 b.n 80033b4 <UART_SetConfig+0x348>
8003112: 2302 movs r3, #2
8003114: 77fb strb r3, [r7, #31]
8003116: e14d b.n 80033b4 <UART_SetConfig+0x348>
8003118: 2304 movs r3, #4
800311a: 77fb strb r3, [r7, #31]
800311c: e14a b.n 80033b4 <UART_SetConfig+0x348>
800311e: 2308 movs r3, #8
8003120: 77fb strb r3, [r7, #31]
8003122: e147 b.n 80033b4 <UART_SetConfig+0x348>
8003124: 2310 movs r3, #16
8003126: 77fb strb r3, [r7, #31]
8003128: e144 b.n 80033b4 <UART_SetConfig+0x348>
800312a: 687b ldr r3, [r7, #4]
800312c: 681b ldr r3, [r3, #0]
800312e: 4a83 ldr r2, [pc, #524] @ (800333c <UART_SetConfig+0x2d0>)
8003130: 4293 cmp r3, r2
8003132: d132 bne.n 800319a <UART_SetConfig+0x12e>
8003134: 4b80 ldr r3, [pc, #512] @ (8003338 <UART_SetConfig+0x2cc>)
8003136: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800313a: f003 030c and.w r3, r3, #12
800313e: 2b0c cmp r3, #12
8003140: d828 bhi.n 8003194 <UART_SetConfig+0x128>
8003142: a201 add r2, pc, #4 @ (adr r2, 8003148 <UART_SetConfig+0xdc>)
8003144: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003148: 0800317d .word 0x0800317d
800314c: 08003195 .word 0x08003195
8003150: 08003195 .word 0x08003195
8003154: 08003195 .word 0x08003195
8003158: 08003189 .word 0x08003189
800315c: 08003195 .word 0x08003195
8003160: 08003195 .word 0x08003195
8003164: 08003195 .word 0x08003195
8003168: 08003183 .word 0x08003183
800316c: 08003195 .word 0x08003195
8003170: 08003195 .word 0x08003195
8003174: 08003195 .word 0x08003195
8003178: 0800318f .word 0x0800318f
800317c: 2300 movs r3, #0
800317e: 77fb strb r3, [r7, #31]
8003180: e118 b.n 80033b4 <UART_SetConfig+0x348>
8003182: 2302 movs r3, #2
8003184: 77fb strb r3, [r7, #31]
8003186: e115 b.n 80033b4 <UART_SetConfig+0x348>
8003188: 2304 movs r3, #4
800318a: 77fb strb r3, [r7, #31]
800318c: e112 b.n 80033b4 <UART_SetConfig+0x348>
800318e: 2308 movs r3, #8
8003190: 77fb strb r3, [r7, #31]
8003192: e10f b.n 80033b4 <UART_SetConfig+0x348>
8003194: 2310 movs r3, #16
8003196: 77fb strb r3, [r7, #31]
8003198: e10c b.n 80033b4 <UART_SetConfig+0x348>
800319a: 687b ldr r3, [r7, #4]
800319c: 681b ldr r3, [r3, #0]
800319e: 4a68 ldr r2, [pc, #416] @ (8003340 <UART_SetConfig+0x2d4>)
80031a0: 4293 cmp r3, r2
80031a2: d120 bne.n 80031e6 <UART_SetConfig+0x17a>
80031a4: 4b64 ldr r3, [pc, #400] @ (8003338 <UART_SetConfig+0x2cc>)
80031a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80031aa: f003 0330 and.w r3, r3, #48 @ 0x30
80031ae: 2b30 cmp r3, #48 @ 0x30
80031b0: d013 beq.n 80031da <UART_SetConfig+0x16e>
80031b2: 2b30 cmp r3, #48 @ 0x30
80031b4: d814 bhi.n 80031e0 <UART_SetConfig+0x174>
80031b6: 2b20 cmp r3, #32
80031b8: d009 beq.n 80031ce <UART_SetConfig+0x162>
80031ba: 2b20 cmp r3, #32
80031bc: d810 bhi.n 80031e0 <UART_SetConfig+0x174>
80031be: 2b00 cmp r3, #0
80031c0: d002 beq.n 80031c8 <UART_SetConfig+0x15c>
80031c2: 2b10 cmp r3, #16
80031c4: d006 beq.n 80031d4 <UART_SetConfig+0x168>
80031c6: e00b b.n 80031e0 <UART_SetConfig+0x174>
80031c8: 2300 movs r3, #0
80031ca: 77fb strb r3, [r7, #31]
80031cc: e0f2 b.n 80033b4 <UART_SetConfig+0x348>
80031ce: 2302 movs r3, #2
80031d0: 77fb strb r3, [r7, #31]
80031d2: e0ef b.n 80033b4 <UART_SetConfig+0x348>
80031d4: 2304 movs r3, #4
80031d6: 77fb strb r3, [r7, #31]
80031d8: e0ec b.n 80033b4 <UART_SetConfig+0x348>
80031da: 2308 movs r3, #8
80031dc: 77fb strb r3, [r7, #31]
80031de: e0e9 b.n 80033b4 <UART_SetConfig+0x348>
80031e0: 2310 movs r3, #16
80031e2: 77fb strb r3, [r7, #31]
80031e4: e0e6 b.n 80033b4 <UART_SetConfig+0x348>
80031e6: 687b ldr r3, [r7, #4]
80031e8: 681b ldr r3, [r3, #0]
80031ea: 4a56 ldr r2, [pc, #344] @ (8003344 <UART_SetConfig+0x2d8>)
80031ec: 4293 cmp r3, r2
80031ee: d120 bne.n 8003232 <UART_SetConfig+0x1c6>
80031f0: 4b51 ldr r3, [pc, #324] @ (8003338 <UART_SetConfig+0x2cc>)
80031f2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80031f6: f003 03c0 and.w r3, r3, #192 @ 0xc0
80031fa: 2bc0 cmp r3, #192 @ 0xc0
80031fc: d013 beq.n 8003226 <UART_SetConfig+0x1ba>
80031fe: 2bc0 cmp r3, #192 @ 0xc0
8003200: d814 bhi.n 800322c <UART_SetConfig+0x1c0>
8003202: 2b80 cmp r3, #128 @ 0x80
8003204: d009 beq.n 800321a <UART_SetConfig+0x1ae>
8003206: 2b80 cmp r3, #128 @ 0x80
8003208: d810 bhi.n 800322c <UART_SetConfig+0x1c0>
800320a: 2b00 cmp r3, #0
800320c: d002 beq.n 8003214 <UART_SetConfig+0x1a8>
800320e: 2b40 cmp r3, #64 @ 0x40
8003210: d006 beq.n 8003220 <UART_SetConfig+0x1b4>
8003212: e00b b.n 800322c <UART_SetConfig+0x1c0>
8003214: 2300 movs r3, #0
8003216: 77fb strb r3, [r7, #31]
8003218: e0cc b.n 80033b4 <UART_SetConfig+0x348>
800321a: 2302 movs r3, #2
800321c: 77fb strb r3, [r7, #31]
800321e: e0c9 b.n 80033b4 <UART_SetConfig+0x348>
8003220: 2304 movs r3, #4
8003222: 77fb strb r3, [r7, #31]
8003224: e0c6 b.n 80033b4 <UART_SetConfig+0x348>
8003226: 2308 movs r3, #8
8003228: 77fb strb r3, [r7, #31]
800322a: e0c3 b.n 80033b4 <UART_SetConfig+0x348>
800322c: 2310 movs r3, #16
800322e: 77fb strb r3, [r7, #31]
8003230: e0c0 b.n 80033b4 <UART_SetConfig+0x348>
8003232: 687b ldr r3, [r7, #4]
8003234: 681b ldr r3, [r3, #0]
8003236: 4a44 ldr r2, [pc, #272] @ (8003348 <UART_SetConfig+0x2dc>)
8003238: 4293 cmp r3, r2
800323a: d125 bne.n 8003288 <UART_SetConfig+0x21c>
800323c: 4b3e ldr r3, [pc, #248] @ (8003338 <UART_SetConfig+0x2cc>)
800323e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003242: f403 7340 and.w r3, r3, #768 @ 0x300
8003246: f5b3 7f40 cmp.w r3, #768 @ 0x300
800324a: d017 beq.n 800327c <UART_SetConfig+0x210>
800324c: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003250: d817 bhi.n 8003282 <UART_SetConfig+0x216>
8003252: f5b3 7f00 cmp.w r3, #512 @ 0x200
8003256: d00b beq.n 8003270 <UART_SetConfig+0x204>
8003258: f5b3 7f00 cmp.w r3, #512 @ 0x200
800325c: d811 bhi.n 8003282 <UART_SetConfig+0x216>
800325e: 2b00 cmp r3, #0
8003260: d003 beq.n 800326a <UART_SetConfig+0x1fe>
8003262: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003266: d006 beq.n 8003276 <UART_SetConfig+0x20a>
8003268: e00b b.n 8003282 <UART_SetConfig+0x216>
800326a: 2300 movs r3, #0
800326c: 77fb strb r3, [r7, #31]
800326e: e0a1 b.n 80033b4 <UART_SetConfig+0x348>
8003270: 2302 movs r3, #2
8003272: 77fb strb r3, [r7, #31]
8003274: e09e b.n 80033b4 <UART_SetConfig+0x348>
8003276: 2304 movs r3, #4
8003278: 77fb strb r3, [r7, #31]
800327a: e09b b.n 80033b4 <UART_SetConfig+0x348>
800327c: 2308 movs r3, #8
800327e: 77fb strb r3, [r7, #31]
8003280: e098 b.n 80033b4 <UART_SetConfig+0x348>
8003282: 2310 movs r3, #16
8003284: 77fb strb r3, [r7, #31]
8003286: e095 b.n 80033b4 <UART_SetConfig+0x348>
8003288: 687b ldr r3, [r7, #4]
800328a: 681b ldr r3, [r3, #0]
800328c: 4a2f ldr r2, [pc, #188] @ (800334c <UART_SetConfig+0x2e0>)
800328e: 4293 cmp r3, r2
8003290: d125 bne.n 80032de <UART_SetConfig+0x272>
8003292: 4b29 ldr r3, [pc, #164] @ (8003338 <UART_SetConfig+0x2cc>)
8003294: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003298: f403 6340 and.w r3, r3, #3072 @ 0xc00
800329c: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80032a0: d017 beq.n 80032d2 <UART_SetConfig+0x266>
80032a2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
80032a6: d817 bhi.n 80032d8 <UART_SetConfig+0x26c>
80032a8: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80032ac: d00b beq.n 80032c6 <UART_SetConfig+0x25a>
80032ae: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80032b2: d811 bhi.n 80032d8 <UART_SetConfig+0x26c>
80032b4: 2b00 cmp r3, #0
80032b6: d003 beq.n 80032c0 <UART_SetConfig+0x254>
80032b8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80032bc: d006 beq.n 80032cc <UART_SetConfig+0x260>
80032be: e00b b.n 80032d8 <UART_SetConfig+0x26c>
80032c0: 2301 movs r3, #1
80032c2: 77fb strb r3, [r7, #31]
80032c4: e076 b.n 80033b4 <UART_SetConfig+0x348>
80032c6: 2302 movs r3, #2
80032c8: 77fb strb r3, [r7, #31]
80032ca: e073 b.n 80033b4 <UART_SetConfig+0x348>
80032cc: 2304 movs r3, #4
80032ce: 77fb strb r3, [r7, #31]
80032d0: e070 b.n 80033b4 <UART_SetConfig+0x348>
80032d2: 2308 movs r3, #8
80032d4: 77fb strb r3, [r7, #31]
80032d6: e06d b.n 80033b4 <UART_SetConfig+0x348>
80032d8: 2310 movs r3, #16
80032da: 77fb strb r3, [r7, #31]
80032dc: e06a b.n 80033b4 <UART_SetConfig+0x348>
80032de: 687b ldr r3, [r7, #4]
80032e0: 681b ldr r3, [r3, #0]
80032e2: 4a1b ldr r2, [pc, #108] @ (8003350 <UART_SetConfig+0x2e4>)
80032e4: 4293 cmp r3, r2
80032e6: d138 bne.n 800335a <UART_SetConfig+0x2ee>
80032e8: 4b13 ldr r3, [pc, #76] @ (8003338 <UART_SetConfig+0x2cc>)
80032ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80032ee: f403 5340 and.w r3, r3, #12288 @ 0x3000
80032f2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80032f6: d017 beq.n 8003328 <UART_SetConfig+0x2bc>
80032f8: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80032fc: d82a bhi.n 8003354 <UART_SetConfig+0x2e8>
80032fe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003302: d00b beq.n 800331c <UART_SetConfig+0x2b0>
8003304: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003308: d824 bhi.n 8003354 <UART_SetConfig+0x2e8>
800330a: 2b00 cmp r3, #0
800330c: d003 beq.n 8003316 <UART_SetConfig+0x2aa>
800330e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003312: d006 beq.n 8003322 <UART_SetConfig+0x2b6>
8003314: e01e b.n 8003354 <UART_SetConfig+0x2e8>
8003316: 2300 movs r3, #0
8003318: 77fb strb r3, [r7, #31]
800331a: e04b b.n 80033b4 <UART_SetConfig+0x348>
800331c: 2302 movs r3, #2
800331e: 77fb strb r3, [r7, #31]
8003320: e048 b.n 80033b4 <UART_SetConfig+0x348>
8003322: 2304 movs r3, #4
8003324: 77fb strb r3, [r7, #31]
8003326: e045 b.n 80033b4 <UART_SetConfig+0x348>
8003328: 2308 movs r3, #8
800332a: 77fb strb r3, [r7, #31]
800332c: e042 b.n 80033b4 <UART_SetConfig+0x348>
800332e: bf00 nop
8003330: efff69f3 .word 0xefff69f3
8003334: 40011000 .word 0x40011000
8003338: 40023800 .word 0x40023800
800333c: 40004400 .word 0x40004400
8003340: 40004800 .word 0x40004800
8003344: 40004c00 .word 0x40004c00
8003348: 40005000 .word 0x40005000
800334c: 40011400 .word 0x40011400
8003350: 40007800 .word 0x40007800
8003354: 2310 movs r3, #16
8003356: 77fb strb r3, [r7, #31]
8003358: e02c b.n 80033b4 <UART_SetConfig+0x348>
800335a: 687b ldr r3, [r7, #4]
800335c: 681b ldr r3, [r3, #0]
800335e: 4a72 ldr r2, [pc, #456] @ (8003528 <UART_SetConfig+0x4bc>)
8003360: 4293 cmp r3, r2
8003362: d125 bne.n 80033b0 <UART_SetConfig+0x344>
8003364: 4b71 ldr r3, [pc, #452] @ (800352c <UART_SetConfig+0x4c0>)
8003366: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800336a: f403 4340 and.w r3, r3, #49152 @ 0xc000
800336e: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003372: d017 beq.n 80033a4 <UART_SetConfig+0x338>
8003374: f5b3 4f40 cmp.w r3, #49152 @ 0xc000
8003378: d817 bhi.n 80033aa <UART_SetConfig+0x33e>
800337a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800337e: d00b beq.n 8003398 <UART_SetConfig+0x32c>
8003380: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8003384: d811 bhi.n 80033aa <UART_SetConfig+0x33e>
8003386: 2b00 cmp r3, #0
8003388: d003 beq.n 8003392 <UART_SetConfig+0x326>
800338a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
800338e: d006 beq.n 800339e <UART_SetConfig+0x332>
8003390: e00b b.n 80033aa <UART_SetConfig+0x33e>
8003392: 2300 movs r3, #0
8003394: 77fb strb r3, [r7, #31]
8003396: e00d b.n 80033b4 <UART_SetConfig+0x348>
8003398: 2302 movs r3, #2
800339a: 77fb strb r3, [r7, #31]
800339c: e00a b.n 80033b4 <UART_SetConfig+0x348>
800339e: 2304 movs r3, #4
80033a0: 77fb strb r3, [r7, #31]
80033a2: e007 b.n 80033b4 <UART_SetConfig+0x348>
80033a4: 2308 movs r3, #8
80033a6: 77fb strb r3, [r7, #31]
80033a8: e004 b.n 80033b4 <UART_SetConfig+0x348>
80033aa: 2310 movs r3, #16
80033ac: 77fb strb r3, [r7, #31]
80033ae: e001 b.n 80033b4 <UART_SetConfig+0x348>
80033b0: 2310 movs r3, #16
80033b2: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80033b4: 687b ldr r3, [r7, #4]
80033b6: 69db ldr r3, [r3, #28]
80033b8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80033bc: d15b bne.n 8003476 <UART_SetConfig+0x40a>
{
switch (clocksource)
80033be: 7ffb ldrb r3, [r7, #31]
80033c0: 2b08 cmp r3, #8
80033c2: d828 bhi.n 8003416 <UART_SetConfig+0x3aa>
80033c4: a201 add r2, pc, #4 @ (adr r2, 80033cc <UART_SetConfig+0x360>)
80033c6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80033ca: bf00 nop
80033cc: 080033f1 .word 0x080033f1
80033d0: 080033f9 .word 0x080033f9
80033d4: 08003401 .word 0x08003401
80033d8: 08003417 .word 0x08003417
80033dc: 08003407 .word 0x08003407
80033e0: 08003417 .word 0x08003417
80033e4: 08003417 .word 0x08003417
80033e8: 08003417 .word 0x08003417
80033ec: 0800340f .word 0x0800340f
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80033f0: f7ff f99e bl 8002730 <HAL_RCC_GetPCLK1Freq>
80033f4: 61b8 str r0, [r7, #24]
break;
80033f6: e013 b.n 8003420 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80033f8: f7ff f9ae bl 8002758 <HAL_RCC_GetPCLK2Freq>
80033fc: 61b8 str r0, [r7, #24]
break;
80033fe: e00f b.n 8003420 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003400: 4b4b ldr r3, [pc, #300] @ (8003530 <UART_SetConfig+0x4c4>)
8003402: 61bb str r3, [r7, #24]
break;
8003404: e00c b.n 8003420 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003406: f7ff f881 bl 800250c <HAL_RCC_GetSysClockFreq>
800340a: 61b8 str r0, [r7, #24]
break;
800340c: e008 b.n 8003420 <UART_SetConfig+0x3b4>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800340e: f44f 4300 mov.w r3, #32768 @ 0x8000
8003412: 61bb str r3, [r7, #24]
break;
8003414: e004 b.n 8003420 <UART_SetConfig+0x3b4>
default:
pclk = 0U;
8003416: 2300 movs r3, #0
8003418: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
800341a: 2301 movs r3, #1
800341c: 77bb strb r3, [r7, #30]
break;
800341e: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8003420: 69bb ldr r3, [r7, #24]
8003422: 2b00 cmp r3, #0
8003424: d074 beq.n 8003510 <UART_SetConfig+0x4a4>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
8003426: 69bb ldr r3, [r7, #24]
8003428: 005a lsls r2, r3, #1
800342a: 687b ldr r3, [r7, #4]
800342c: 685b ldr r3, [r3, #4]
800342e: 085b lsrs r3, r3, #1
8003430: 441a add r2, r3
8003432: 687b ldr r3, [r7, #4]
8003434: 685b ldr r3, [r3, #4]
8003436: fbb2 f3f3 udiv r3, r2, r3
800343a: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800343c: 693b ldr r3, [r7, #16]
800343e: 2b0f cmp r3, #15
8003440: d916 bls.n 8003470 <UART_SetConfig+0x404>
8003442: 693b ldr r3, [r7, #16]
8003444: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003448: d212 bcs.n 8003470 <UART_SetConfig+0x404>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800344a: 693b ldr r3, [r7, #16]
800344c: b29b uxth r3, r3
800344e: f023 030f bic.w r3, r3, #15
8003452: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8003454: 693b ldr r3, [r7, #16]
8003456: 085b lsrs r3, r3, #1
8003458: b29b uxth r3, r3
800345a: f003 0307 and.w r3, r3, #7
800345e: b29a uxth r2, r3
8003460: 89fb ldrh r3, [r7, #14]
8003462: 4313 orrs r3, r2
8003464: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
8003466: 687b ldr r3, [r7, #4]
8003468: 681b ldr r3, [r3, #0]
800346a: 89fa ldrh r2, [r7, #14]
800346c: 60da str r2, [r3, #12]
800346e: e04f b.n 8003510 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
8003470: 2301 movs r3, #1
8003472: 77bb strb r3, [r7, #30]
8003474: e04c b.n 8003510 <UART_SetConfig+0x4a4>
}
}
}
else
{
switch (clocksource)
8003476: 7ffb ldrb r3, [r7, #31]
8003478: 2b08 cmp r3, #8
800347a: d828 bhi.n 80034ce <UART_SetConfig+0x462>
800347c: a201 add r2, pc, #4 @ (adr r2, 8003484 <UART_SetConfig+0x418>)
800347e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003482: bf00 nop
8003484: 080034a9 .word 0x080034a9
8003488: 080034b1 .word 0x080034b1
800348c: 080034b9 .word 0x080034b9
8003490: 080034cf .word 0x080034cf
8003494: 080034bf .word 0x080034bf
8003498: 080034cf .word 0x080034cf
800349c: 080034cf .word 0x080034cf
80034a0: 080034cf .word 0x080034cf
80034a4: 080034c7 .word 0x080034c7
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80034a8: f7ff f942 bl 8002730 <HAL_RCC_GetPCLK1Freq>
80034ac: 61b8 str r0, [r7, #24]
break;
80034ae: e013 b.n 80034d8 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
80034b0: f7ff f952 bl 8002758 <HAL_RCC_GetPCLK2Freq>
80034b4: 61b8 str r0, [r7, #24]
break;
80034b6: e00f b.n 80034d8 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80034b8: 4b1d ldr r3, [pc, #116] @ (8003530 <UART_SetConfig+0x4c4>)
80034ba: 61bb str r3, [r7, #24]
break;
80034bc: e00c b.n 80034d8 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80034be: f7ff f825 bl 800250c <HAL_RCC_GetSysClockFreq>
80034c2: 61b8 str r0, [r7, #24]
break;
80034c4: e008 b.n 80034d8 <UART_SetConfig+0x46c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80034c6: f44f 4300 mov.w r3, #32768 @ 0x8000
80034ca: 61bb str r3, [r7, #24]
break;
80034cc: e004 b.n 80034d8 <UART_SetConfig+0x46c>
default:
pclk = 0U;
80034ce: 2300 movs r3, #0
80034d0: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
80034d2: 2301 movs r3, #1
80034d4: 77bb strb r3, [r7, #30]
break;
80034d6: bf00 nop
}
if (pclk != 0U)
80034d8: 69bb ldr r3, [r7, #24]
80034da: 2b00 cmp r3, #0
80034dc: d018 beq.n 8003510 <UART_SetConfig+0x4a4>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
80034de: 687b ldr r3, [r7, #4]
80034e0: 685b ldr r3, [r3, #4]
80034e2: 085a lsrs r2, r3, #1
80034e4: 69bb ldr r3, [r7, #24]
80034e6: 441a add r2, r3
80034e8: 687b ldr r3, [r7, #4]
80034ea: 685b ldr r3, [r3, #4]
80034ec: fbb2 f3f3 udiv r3, r2, r3
80034f0: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80034f2: 693b ldr r3, [r7, #16]
80034f4: 2b0f cmp r3, #15
80034f6: d909 bls.n 800350c <UART_SetConfig+0x4a0>
80034f8: 693b ldr r3, [r7, #16]
80034fa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80034fe: d205 bcs.n 800350c <UART_SetConfig+0x4a0>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8003500: 693b ldr r3, [r7, #16]
8003502: b29a uxth r2, r3
8003504: 687b ldr r3, [r7, #4]
8003506: 681b ldr r3, [r3, #0]
8003508: 60da str r2, [r3, #12]
800350a: e001 b.n 8003510 <UART_SetConfig+0x4a4>
}
else
{
ret = HAL_ERROR;
800350c: 2301 movs r3, #1
800350e: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
8003510: 687b ldr r3, [r7, #4]
8003512: 2200 movs r2, #0
8003514: 669a str r2, [r3, #104] @ 0x68
huart->TxISR = NULL;
8003516: 687b ldr r3, [r7, #4]
8003518: 2200 movs r2, #0
800351a: 66da str r2, [r3, #108] @ 0x6c
return ret;
800351c: 7fbb ldrb r3, [r7, #30]
}
800351e: 4618 mov r0, r3
8003520: 3720 adds r7, #32
8003522: 46bd mov sp, r7
8003524: bd80 pop {r7, pc}
8003526: bf00 nop
8003528: 40007c00 .word 0x40007c00
800352c: 40023800 .word 0x40023800
8003530: 00f42400 .word 0x00f42400
08003534 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8003534: b480 push {r7}
8003536: b083 sub sp, #12
8003538: af00 add r7, sp, #0
800353a: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
800353c: 687b ldr r3, [r7, #4]
800353e: 6a5b ldr r3, [r3, #36] @ 0x24
8003540: f003 0308 and.w r3, r3, #8
8003544: 2b00 cmp r3, #0
8003546: d00a beq.n 800355e <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8003548: 687b ldr r3, [r7, #4]
800354a: 681b ldr r3, [r3, #0]
800354c: 685b ldr r3, [r3, #4]
800354e: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8003552: 687b ldr r3, [r7, #4]
8003554: 6b5a ldr r2, [r3, #52] @ 0x34
8003556: 687b ldr r3, [r7, #4]
8003558: 681b ldr r3, [r3, #0]
800355a: 430a orrs r2, r1
800355c: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
800355e: 687b ldr r3, [r7, #4]
8003560: 6a5b ldr r3, [r3, #36] @ 0x24
8003562: f003 0301 and.w r3, r3, #1
8003566: 2b00 cmp r3, #0
8003568: d00a beq.n 8003580 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800356a: 687b ldr r3, [r7, #4]
800356c: 681b ldr r3, [r3, #0]
800356e: 685b ldr r3, [r3, #4]
8003570: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8003574: 687b ldr r3, [r7, #4]
8003576: 6a9a ldr r2, [r3, #40] @ 0x28
8003578: 687b ldr r3, [r7, #4]
800357a: 681b ldr r3, [r3, #0]
800357c: 430a orrs r2, r1
800357e: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8003580: 687b ldr r3, [r7, #4]
8003582: 6a5b ldr r3, [r3, #36] @ 0x24
8003584: f003 0302 and.w r3, r3, #2
8003588: 2b00 cmp r3, #0
800358a: d00a beq.n 80035a2 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
800358c: 687b ldr r3, [r7, #4]
800358e: 681b ldr r3, [r3, #0]
8003590: 685b ldr r3, [r3, #4]
8003592: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8003596: 687b ldr r3, [r7, #4]
8003598: 6ada ldr r2, [r3, #44] @ 0x2c
800359a: 687b ldr r3, [r7, #4]
800359c: 681b ldr r3, [r3, #0]
800359e: 430a orrs r2, r1
80035a0: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80035a2: 687b ldr r3, [r7, #4]
80035a4: 6a5b ldr r3, [r3, #36] @ 0x24
80035a6: f003 0304 and.w r3, r3, #4
80035aa: 2b00 cmp r3, #0
80035ac: d00a beq.n 80035c4 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80035ae: 687b ldr r3, [r7, #4]
80035b0: 681b ldr r3, [r3, #0]
80035b2: 685b ldr r3, [r3, #4]
80035b4: f423 2180 bic.w r1, r3, #262144 @ 0x40000
80035b8: 687b ldr r3, [r7, #4]
80035ba: 6b1a ldr r2, [r3, #48] @ 0x30
80035bc: 687b ldr r3, [r7, #4]
80035be: 681b ldr r3, [r3, #0]
80035c0: 430a orrs r2, r1
80035c2: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80035c4: 687b ldr r3, [r7, #4]
80035c6: 6a5b ldr r3, [r3, #36] @ 0x24
80035c8: f003 0310 and.w r3, r3, #16
80035cc: 2b00 cmp r3, #0
80035ce: d00a beq.n 80035e6 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80035d0: 687b ldr r3, [r7, #4]
80035d2: 681b ldr r3, [r3, #0]
80035d4: 689b ldr r3, [r3, #8]
80035d6: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80035da: 687b ldr r3, [r7, #4]
80035dc: 6b9a ldr r2, [r3, #56] @ 0x38
80035de: 687b ldr r3, [r7, #4]
80035e0: 681b ldr r3, [r3, #0]
80035e2: 430a orrs r2, r1
80035e4: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80035e6: 687b ldr r3, [r7, #4]
80035e8: 6a5b ldr r3, [r3, #36] @ 0x24
80035ea: f003 0320 and.w r3, r3, #32
80035ee: 2b00 cmp r3, #0
80035f0: d00a beq.n 8003608 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80035f2: 687b ldr r3, [r7, #4]
80035f4: 681b ldr r3, [r3, #0]
80035f6: 689b ldr r3, [r3, #8]
80035f8: f423 5100 bic.w r1, r3, #8192 @ 0x2000
80035fc: 687b ldr r3, [r7, #4]
80035fe: 6bda ldr r2, [r3, #60] @ 0x3c
8003600: 687b ldr r3, [r7, #4]
8003602: 681b ldr r3, [r3, #0]
8003604: 430a orrs r2, r1
8003606: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8003608: 687b ldr r3, [r7, #4]
800360a: 6a5b ldr r3, [r3, #36] @ 0x24
800360c: f003 0340 and.w r3, r3, #64 @ 0x40
8003610: 2b00 cmp r3, #0
8003612: d01a beq.n 800364a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8003614: 687b ldr r3, [r7, #4]
8003616: 681b ldr r3, [r3, #0]
8003618: 685b ldr r3, [r3, #4]
800361a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
800361e: 687b ldr r3, [r7, #4]
8003620: 6c1a ldr r2, [r3, #64] @ 0x40
8003622: 687b ldr r3, [r7, #4]
8003624: 681b ldr r3, [r3, #0]
8003626: 430a orrs r2, r1
8003628: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
800362a: 687b ldr r3, [r7, #4]
800362c: 6c1b ldr r3, [r3, #64] @ 0x40
800362e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8003632: d10a bne.n 800364a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8003634: 687b ldr r3, [r7, #4]
8003636: 681b ldr r3, [r3, #0]
8003638: 685b ldr r3, [r3, #4]
800363a: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
800363e: 687b ldr r3, [r7, #4]
8003640: 6c5a ldr r2, [r3, #68] @ 0x44
8003642: 687b ldr r3, [r7, #4]
8003644: 681b ldr r3, [r3, #0]
8003646: 430a orrs r2, r1
8003648: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
800364a: 687b ldr r3, [r7, #4]
800364c: 6a5b ldr r3, [r3, #36] @ 0x24
800364e: f003 0380 and.w r3, r3, #128 @ 0x80
8003652: 2b00 cmp r3, #0
8003654: d00a beq.n 800366c <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8003656: 687b ldr r3, [r7, #4]
8003658: 681b ldr r3, [r3, #0]
800365a: 685b ldr r3, [r3, #4]
800365c: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8003660: 687b ldr r3, [r7, #4]
8003662: 6c9a ldr r2, [r3, #72] @ 0x48
8003664: 687b ldr r3, [r7, #4]
8003666: 681b ldr r3, [r3, #0]
8003668: 430a orrs r2, r1
800366a: 605a str r2, [r3, #4]
}
}
800366c: bf00 nop
800366e: 370c adds r7, #12
8003670: 46bd mov sp, r7
8003672: f85d 7b04 ldr.w r7, [sp], #4
8003676: 4770 bx lr
08003678 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8003678: b580 push {r7, lr}
800367a: b098 sub sp, #96 @ 0x60
800367c: af02 add r7, sp, #8
800367e: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003680: 687b ldr r3, [r7, #4]
8003682: 2200 movs r2, #0
8003684: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003688: f7fd fbc8 bl 8000e1c <HAL_GetTick>
800368c: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800368e: 687b ldr r3, [r7, #4]
8003690: 681b ldr r3, [r3, #0]
8003692: 681b ldr r3, [r3, #0]
8003694: f003 0308 and.w r3, r3, #8
8003698: 2b08 cmp r3, #8
800369a: d12e bne.n 80036fa <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800369c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80036a0: 9300 str r3, [sp, #0]
80036a2: 6d7b ldr r3, [r7, #84] @ 0x54
80036a4: 2200 movs r2, #0
80036a6: f44f 1100 mov.w r1, #2097152 @ 0x200000
80036aa: 6878 ldr r0, [r7, #4]
80036ac: f000 f88c bl 80037c8 <UART_WaitOnFlagUntilTimeout>
80036b0: 4603 mov r3, r0
80036b2: 2b00 cmp r3, #0
80036b4: d021 beq.n 80036fa <UART_CheckIdleState+0x82>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
80036b6: 687b ldr r3, [r7, #4]
80036b8: 681b ldr r3, [r3, #0]
80036ba: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80036bc: 6bbb ldr r3, [r7, #56] @ 0x38
80036be: e853 3f00 ldrex r3, [r3]
80036c2: 637b str r3, [r7, #52] @ 0x34
return(result);
80036c4: 6b7b ldr r3, [r7, #52] @ 0x34
80036c6: f023 0380 bic.w r3, r3, #128 @ 0x80
80036ca: 653b str r3, [r7, #80] @ 0x50
80036cc: 687b ldr r3, [r7, #4]
80036ce: 681b ldr r3, [r3, #0]
80036d0: 461a mov r2, r3
80036d2: 6d3b ldr r3, [r7, #80] @ 0x50
80036d4: 647b str r3, [r7, #68] @ 0x44
80036d6: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80036d8: 6c39 ldr r1, [r7, #64] @ 0x40
80036da: 6c7a ldr r2, [r7, #68] @ 0x44
80036dc: e841 2300 strex r3, r2, [r1]
80036e0: 63fb str r3, [r7, #60] @ 0x3c
return(result);
80036e2: 6bfb ldr r3, [r7, #60] @ 0x3c
80036e4: 2b00 cmp r3, #0
80036e6: d1e6 bne.n 80036b6 <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
80036e8: 687b ldr r3, [r7, #4]
80036ea: 2220 movs r2, #32
80036ec: 67da str r2, [r3, #124] @ 0x7c
__HAL_UNLOCK(huart);
80036ee: 687b ldr r3, [r7, #4]
80036f0: 2200 movs r2, #0
80036f2: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
80036f6: 2303 movs r3, #3
80036f8: e062 b.n 80037c0 <UART_CheckIdleState+0x148>
}
}
#if defined(USART_ISR_REACK)
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80036fa: 687b ldr r3, [r7, #4]
80036fc: 681b ldr r3, [r3, #0]
80036fe: 681b ldr r3, [r3, #0]
8003700: f003 0304 and.w r3, r3, #4
8003704: 2b04 cmp r3, #4
8003706: d149 bne.n 800379c <UART_CheckIdleState+0x124>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8003708: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
800370c: 9300 str r3, [sp, #0]
800370e: 6d7b ldr r3, [r7, #84] @ 0x54
8003710: 2200 movs r2, #0
8003712: f44f 0180 mov.w r1, #4194304 @ 0x400000
8003716: 6878 ldr r0, [r7, #4]
8003718: f000 f856 bl 80037c8 <UART_WaitOnFlagUntilTimeout>
800371c: 4603 mov r3, r0
800371e: 2b00 cmp r3, #0
8003720: d03c beq.n 800379c <UART_CheckIdleState+0x124>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8003722: 687b ldr r3, [r7, #4]
8003724: 681b ldr r3, [r3, #0]
8003726: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003728: 6a7b ldr r3, [r7, #36] @ 0x24
800372a: e853 3f00 ldrex r3, [r3]
800372e: 623b str r3, [r7, #32]
return(result);
8003730: 6a3b ldr r3, [r7, #32]
8003732: f423 7390 bic.w r3, r3, #288 @ 0x120
8003736: 64fb str r3, [r7, #76] @ 0x4c
8003738: 687b ldr r3, [r7, #4]
800373a: 681b ldr r3, [r3, #0]
800373c: 461a mov r2, r3
800373e: 6cfb ldr r3, [r7, #76] @ 0x4c
8003740: 633b str r3, [r7, #48] @ 0x30
8003742: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003744: 6af9 ldr r1, [r7, #44] @ 0x2c
8003746: 6b3a ldr r2, [r7, #48] @ 0x30
8003748: e841 2300 strex r3, r2, [r1]
800374c: 62bb str r3, [r7, #40] @ 0x28
return(result);
800374e: 6abb ldr r3, [r7, #40] @ 0x28
8003750: 2b00 cmp r3, #0
8003752: d1e6 bne.n 8003722 <UART_CheckIdleState+0xaa>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8003754: 687b ldr r3, [r7, #4]
8003756: 681b ldr r3, [r3, #0]
8003758: 3308 adds r3, #8
800375a: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800375c: 693b ldr r3, [r7, #16]
800375e: e853 3f00 ldrex r3, [r3]
8003762: 60fb str r3, [r7, #12]
return(result);
8003764: 68fb ldr r3, [r7, #12]
8003766: f023 0301 bic.w r3, r3, #1
800376a: 64bb str r3, [r7, #72] @ 0x48
800376c: 687b ldr r3, [r7, #4]
800376e: 681b ldr r3, [r3, #0]
8003770: 3308 adds r3, #8
8003772: 6cba ldr r2, [r7, #72] @ 0x48
8003774: 61fa str r2, [r7, #28]
8003776: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003778: 69b9 ldr r1, [r7, #24]
800377a: 69fa ldr r2, [r7, #28]
800377c: e841 2300 strex r3, r2, [r1]
8003780: 617b str r3, [r7, #20]
return(result);
8003782: 697b ldr r3, [r7, #20]
8003784: 2b00 cmp r3, #0
8003786: d1e5 bne.n 8003754 <UART_CheckIdleState+0xdc>
huart->RxState = HAL_UART_STATE_READY;
8003788: 687b ldr r3, [r7, #4]
800378a: 2220 movs r2, #32
800378c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
__HAL_UNLOCK(huart);
8003790: 687b ldr r3, [r7, #4]
8003792: 2200 movs r2, #0
8003794: f883 2078 strb.w r2, [r3, #120] @ 0x78
/* Timeout occurred */
return HAL_TIMEOUT;
8003798: 2303 movs r3, #3
800379a: e011 b.n 80037c0 <UART_CheckIdleState+0x148>
}
}
#endif /* USART_ISR_REACK */
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800379c: 687b ldr r3, [r7, #4]
800379e: 2220 movs r2, #32
80037a0: 67da str r2, [r3, #124] @ 0x7c
huart->RxState = HAL_UART_STATE_READY;
80037a2: 687b ldr r3, [r7, #4]
80037a4: 2220 movs r2, #32
80037a6: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80037aa: 687b ldr r3, [r7, #4]
80037ac: 2200 movs r2, #0
80037ae: 661a str r2, [r3, #96] @ 0x60
huart->RxEventType = HAL_UART_RXEVENT_TC;
80037b0: 687b ldr r3, [r7, #4]
80037b2: 2200 movs r2, #0
80037b4: 665a str r2, [r3, #100] @ 0x64
__HAL_UNLOCK(huart);
80037b6: 687b ldr r3, [r7, #4]
80037b8: 2200 movs r2, #0
80037ba: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_OK;
80037be: 2300 movs r3, #0
}
80037c0: 4618 mov r0, r3
80037c2: 3758 adds r7, #88 @ 0x58
80037c4: 46bd mov sp, r7
80037c6: bd80 pop {r7, pc}
080037c8 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80037c8: b580 push {r7, lr}
80037ca: b084 sub sp, #16
80037cc: af00 add r7, sp, #0
80037ce: 60f8 str r0, [r7, #12]
80037d0: 60b9 str r1, [r7, #8]
80037d2: 603b str r3, [r7, #0]
80037d4: 4613 mov r3, r2
80037d6: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80037d8: e04f b.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80037da: 69bb ldr r3, [r7, #24]
80037dc: f1b3 3fff cmp.w r3, #4294967295
80037e0: d04b beq.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80037e2: f7fd fb1b bl 8000e1c <HAL_GetTick>
80037e6: 4602 mov r2, r0
80037e8: 683b ldr r3, [r7, #0]
80037ea: 1ad3 subs r3, r2, r3
80037ec: 69ba ldr r2, [r7, #24]
80037ee: 429a cmp r2, r3
80037f0: d302 bcc.n 80037f8 <UART_WaitOnFlagUntilTimeout+0x30>
80037f2: 69bb ldr r3, [r7, #24]
80037f4: 2b00 cmp r3, #0
80037f6: d101 bne.n 80037fc <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
80037f8: 2303 movs r3, #3
80037fa: e04e b.n 800389a <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80037fc: 68fb ldr r3, [r7, #12]
80037fe: 681b ldr r3, [r3, #0]
8003800: 681b ldr r3, [r3, #0]
8003802: f003 0304 and.w r3, r3, #4
8003806: 2b00 cmp r3, #0
8003808: d037 beq.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
800380a: 68bb ldr r3, [r7, #8]
800380c: 2b80 cmp r3, #128 @ 0x80
800380e: d034 beq.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
8003810: 68bb ldr r3, [r7, #8]
8003812: 2b40 cmp r3, #64 @ 0x40
8003814: d031 beq.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8003816: 68fb ldr r3, [r7, #12]
8003818: 681b ldr r3, [r3, #0]
800381a: 69db ldr r3, [r3, #28]
800381c: f003 0308 and.w r3, r3, #8
8003820: 2b08 cmp r3, #8
8003822: d110 bne.n 8003846 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8003824: 68fb ldr r3, [r7, #12]
8003826: 681b ldr r3, [r3, #0]
8003828: 2208 movs r2, #8
800382a: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
800382c: 68f8 ldr r0, [r7, #12]
800382e: f000 f838 bl 80038a2 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8003832: 68fb ldr r3, [r7, #12]
8003834: 2208 movs r2, #8
8003836: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
800383a: 68fb ldr r3, [r7, #12]
800383c: 2200 movs r2, #0
800383e: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_ERROR;
8003842: 2301 movs r3, #1
8003844: e029 b.n 800389a <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8003846: 68fb ldr r3, [r7, #12]
8003848: 681b ldr r3, [r3, #0]
800384a: 69db ldr r3, [r3, #28]
800384c: f403 6300 and.w r3, r3, #2048 @ 0x800
8003850: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003854: d111 bne.n 800387a <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8003856: 68fb ldr r3, [r7, #12]
8003858: 681b ldr r3, [r3, #0]
800385a: f44f 6200 mov.w r2, #2048 @ 0x800
800385e: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8003860: 68f8 ldr r0, [r7, #12]
8003862: f000 f81e bl 80038a2 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8003866: 68fb ldr r3, [r7, #12]
8003868: 2220 movs r2, #32
800386a: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Process Unlocked */
__HAL_UNLOCK(huart);
800386e: 68fb ldr r3, [r7, #12]
8003870: 2200 movs r2, #0
8003872: f883 2078 strb.w r2, [r3, #120] @ 0x78
return HAL_TIMEOUT;
8003876: 2303 movs r3, #3
8003878: e00f b.n 800389a <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800387a: 68fb ldr r3, [r7, #12]
800387c: 681b ldr r3, [r3, #0]
800387e: 69da ldr r2, [r3, #28]
8003880: 68bb ldr r3, [r7, #8]
8003882: 4013 ands r3, r2
8003884: 68ba ldr r2, [r7, #8]
8003886: 429a cmp r2, r3
8003888: bf0c ite eq
800388a: 2301 moveq r3, #1
800388c: 2300 movne r3, #0
800388e: b2db uxtb r3, r3
8003890: 461a mov r2, r3
8003892: 79fb ldrb r3, [r7, #7]
8003894: 429a cmp r2, r3
8003896: d0a0 beq.n 80037da <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8003898: 2300 movs r3, #0
}
800389a: 4618 mov r0, r3
800389c: 3710 adds r7, #16
800389e: 46bd mov sp, r7
80038a0: bd80 pop {r7, pc}
080038a2 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80038a2: b480 push {r7}
80038a4: b095 sub sp, #84 @ 0x54
80038a6: af00 add r7, sp, #0
80038a8: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80038aa: 687b ldr r3, [r7, #4]
80038ac: 681b ldr r3, [r3, #0]
80038ae: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80038b0: 6b7b ldr r3, [r7, #52] @ 0x34
80038b2: e853 3f00 ldrex r3, [r3]
80038b6: 633b str r3, [r7, #48] @ 0x30
return(result);
80038b8: 6b3b ldr r3, [r7, #48] @ 0x30
80038ba: f423 7390 bic.w r3, r3, #288 @ 0x120
80038be: 64fb str r3, [r7, #76] @ 0x4c
80038c0: 687b ldr r3, [r7, #4]
80038c2: 681b ldr r3, [r3, #0]
80038c4: 461a mov r2, r3
80038c6: 6cfb ldr r3, [r7, #76] @ 0x4c
80038c8: 643b str r3, [r7, #64] @ 0x40
80038ca: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80038cc: 6bf9 ldr r1, [r7, #60] @ 0x3c
80038ce: 6c3a ldr r2, [r7, #64] @ 0x40
80038d0: e841 2300 strex r3, r2, [r1]
80038d4: 63bb str r3, [r7, #56] @ 0x38
return(result);
80038d6: 6bbb ldr r3, [r7, #56] @ 0x38
80038d8: 2b00 cmp r3, #0
80038da: d1e6 bne.n 80038aa <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80038dc: 687b ldr r3, [r7, #4]
80038de: 681b ldr r3, [r3, #0]
80038e0: 3308 adds r3, #8
80038e2: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80038e4: 6a3b ldr r3, [r7, #32]
80038e6: e853 3f00 ldrex r3, [r3]
80038ea: 61fb str r3, [r7, #28]
return(result);
80038ec: 69fb ldr r3, [r7, #28]
80038ee: f023 0301 bic.w r3, r3, #1
80038f2: 64bb str r3, [r7, #72] @ 0x48
80038f4: 687b ldr r3, [r7, #4]
80038f6: 681b ldr r3, [r3, #0]
80038f8: 3308 adds r3, #8
80038fa: 6cba ldr r2, [r7, #72] @ 0x48
80038fc: 62fa str r2, [r7, #44] @ 0x2c
80038fe: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003900: 6ab9 ldr r1, [r7, #40] @ 0x28
8003902: 6afa ldr r2, [r7, #44] @ 0x2c
8003904: e841 2300 strex r3, r2, [r1]
8003908: 627b str r3, [r7, #36] @ 0x24
return(result);
800390a: 6a7b ldr r3, [r7, #36] @ 0x24
800390c: 2b00 cmp r3, #0
800390e: d1e5 bne.n 80038dc <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8003910: 687b ldr r3, [r7, #4]
8003912: 6e1b ldr r3, [r3, #96] @ 0x60
8003914: 2b01 cmp r3, #1
8003916: d118 bne.n 800394a <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8003918: 687b ldr r3, [r7, #4]
800391a: 681b ldr r3, [r3, #0]
800391c: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800391e: 68fb ldr r3, [r7, #12]
8003920: e853 3f00 ldrex r3, [r3]
8003924: 60bb str r3, [r7, #8]
return(result);
8003926: 68bb ldr r3, [r7, #8]
8003928: f023 0310 bic.w r3, r3, #16
800392c: 647b str r3, [r7, #68] @ 0x44
800392e: 687b ldr r3, [r7, #4]
8003930: 681b ldr r3, [r3, #0]
8003932: 461a mov r2, r3
8003934: 6c7b ldr r3, [r7, #68] @ 0x44
8003936: 61bb str r3, [r7, #24]
8003938: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800393a: 6979 ldr r1, [r7, #20]
800393c: 69ba ldr r2, [r7, #24]
800393e: e841 2300 strex r3, r2, [r1]
8003942: 613b str r3, [r7, #16]
return(result);
8003944: 693b ldr r3, [r7, #16]
8003946: 2b00 cmp r3, #0
8003948: d1e6 bne.n 8003918 <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800394a: 687b ldr r3, [r7, #4]
800394c: 2220 movs r2, #32
800394e: f8c3 2080 str.w r2, [r3, #128] @ 0x80
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003952: 687b ldr r3, [r7, #4]
8003954: 2200 movs r2, #0
8003956: 661a str r2, [r3, #96] @ 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8003958: 687b ldr r3, [r7, #4]
800395a: 2200 movs r2, #0
800395c: 669a str r2, [r3, #104] @ 0x68
}
800395e: bf00 nop
8003960: 3754 adds r7, #84 @ 0x54
8003962: 46bd mov sp, r7
8003964: f85d 7b04 ldr.w r7, [sp], #4
8003968: 4770 bx lr
...
0800396c <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
800396c: b084 sub sp, #16
800396e: b580 push {r7, lr}
8003970: b084 sub sp, #16
8003972: af00 add r7, sp, #0
8003974: 6078 str r0, [r7, #4]
8003976: f107 001c add.w r0, r7, #28
800397a: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
800397e: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
8003982: 2b01 cmp r3, #1
8003984: d121 bne.n 80039ca <USB_CoreInit+0x5e>
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
8003986: 687b ldr r3, [r7, #4]
8003988: 6b9b ldr r3, [r3, #56] @ 0x38
800398a: f423 3280 bic.w r2, r3, #65536 @ 0x10000
800398e: 687b ldr r3, [r7, #4]
8003990: 639a str r2, [r3, #56] @ 0x38
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
8003992: 687b ldr r3, [r7, #4]
8003994: 68da ldr r2, [r3, #12]
8003996: 4b21 ldr r3, [pc, #132] @ (8003a1c <USB_CoreInit+0xb0>)
8003998: 4013 ands r3, r2
800399a: 687a ldr r2, [r7, #4]
800399c: 60d3 str r3, [r2, #12]
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) ||
defined(STM32F732xx) || defined(STM32F733xx) */
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
800399e: 687b ldr r3, [r7, #4]
80039a0: 68db ldr r3, [r3, #12]
80039a2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80039a6: 687b ldr r3, [r7, #4]
80039a8: 60da str r2, [r3, #12]
if (cfg.use_external_vbus == 1U)
80039aa: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
80039ae: 2b01 cmp r3, #1
80039b0: d105 bne.n 80039be <USB_CoreInit+0x52>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
80039b2: 687b ldr r3, [r7, #4]
80039b4: 68db ldr r3, [r3, #12]
80039b6: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
80039ba: 687b ldr r3, [r7, #4]
80039bc: 60da str r2, [r3, #12]
}
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
80039be: 6878 ldr r0, [r7, #4]
80039c0: f000 fa92 bl 8003ee8 <USB_CoreReset>
80039c4: 4603 mov r3, r0
80039c6: 73fb strb r3, [r7, #15]
80039c8: e010 b.n 80039ec <USB_CoreInit+0x80>
#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) ||
defined(STM32F732xx) || defined(STM32F733xx) */
else /* FS interface (embedded Phy) */
{
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
80039ca: 687b ldr r3, [r7, #4]
80039cc: 68db ldr r3, [r3, #12]
80039ce: f043 0240 orr.w r2, r3, #64 @ 0x40
80039d2: 687b ldr r3, [r7, #4]
80039d4: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
80039d6: 6878 ldr r0, [r7, #4]
80039d8: f000 fa86 bl 8003ee8 <USB_CoreReset>
80039dc: 4603 mov r3, r0
80039de: 73fb strb r3, [r7, #15]
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
80039e0: 687b ldr r3, [r7, #4]
80039e2: 6b9b ldr r3, [r3, #56] @ 0x38
80039e4: f443 3280 orr.w r2, r3, #65536 @ 0x10000
80039e8: 687b ldr r3, [r7, #4]
80039ea: 639a str r2, [r3, #56] @ 0x38
}
if (cfg.dma_enable == 1U)
80039ec: 7fbb ldrb r3, [r7, #30]
80039ee: 2b01 cmp r3, #1
80039f0: d10b bne.n 8003a0a <USB_CoreInit+0x9e>
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
80039f2: 687b ldr r3, [r7, #4]
80039f4: 689b ldr r3, [r3, #8]
80039f6: f043 0206 orr.w r2, r3, #6
80039fa: 687b ldr r3, [r7, #4]
80039fc: 609a str r2, [r3, #8]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
80039fe: 687b ldr r3, [r7, #4]
8003a00: 689b ldr r3, [r3, #8]
8003a02: f043 0220 orr.w r2, r3, #32
8003a06: 687b ldr r3, [r7, #4]
8003a08: 609a str r2, [r3, #8]
}
return ret;
8003a0a: 7bfb ldrb r3, [r7, #15]
}
8003a0c: 4618 mov r0, r3
8003a0e: 3710 adds r7, #16
8003a10: 46bd mov sp, r7
8003a12: e8bd 4080 ldmia.w sp!, {r7, lr}
8003a16: b004 add sp, #16
8003a18: 4770 bx lr
8003a1a: bf00 nop
8003a1c: ffbdffbf .word 0xffbdffbf
08003a20 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
8003a20: b480 push {r7}
8003a22: b083 sub sp, #12
8003a24: af00 add r7, sp, #0
8003a26: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 689b ldr r3, [r3, #8]
8003a2c: f023 0201 bic.w r2, r3, #1
8003a30: 687b ldr r3, [r7, #4]
8003a32: 609a str r2, [r3, #8]
return HAL_OK;
8003a34: 2300 movs r3, #0
}
8003a36: 4618 mov r0, r3
8003a38: 370c adds r7, #12
8003a3a: 46bd mov sp, r7
8003a3c: f85d 7b04 ldr.w r7, [sp], #4
8003a40: 4770 bx lr
08003a42 <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
8003a42: b580 push {r7, lr}
8003a44: b084 sub sp, #16
8003a46: af00 add r7, sp, #0
8003a48: 6078 str r0, [r7, #4]
8003a4a: 460b mov r3, r1
8003a4c: 70fb strb r3, [r7, #3]
uint32_t ms = 0U;
8003a4e: 2300 movs r3, #0
8003a50: 60fb str r3, [r7, #12]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
8003a52: 687b ldr r3, [r7, #4]
8003a54: 68db ldr r3, [r3, #12]
8003a56: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
8003a5a: 687b ldr r3, [r7, #4]
8003a5c: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
8003a5e: 78fb ldrb r3, [r7, #3]
8003a60: 2b01 cmp r3, #1
8003a62: d115 bne.n 8003a90 <USB_SetCurrentMode+0x4e>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
8003a64: 687b ldr r3, [r7, #4]
8003a66: 68db ldr r3, [r3, #12]
8003a68: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8003a70: 200a movs r0, #10
8003a72: f7fd f9df bl 8000e34 <HAL_Delay>
ms += 10U;
8003a76: 68fb ldr r3, [r7, #12]
8003a78: 330a adds r3, #10
8003a7a: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8003a7c: 6878 ldr r0, [r7, #4]
8003a7e: f000 fa25 bl 8003ecc <USB_GetMode>
8003a82: 4603 mov r3, r0
8003a84: 2b01 cmp r3, #1
8003a86: d01e beq.n 8003ac6 <USB_SetCurrentMode+0x84>
8003a88: 68fb ldr r3, [r7, #12]
8003a8a: 2bc7 cmp r3, #199 @ 0xc7
8003a8c: d9f0 bls.n 8003a70 <USB_SetCurrentMode+0x2e>
8003a8e: e01a b.n 8003ac6 <USB_SetCurrentMode+0x84>
}
else if (mode == USB_DEVICE_MODE)
8003a90: 78fb ldrb r3, [r7, #3]
8003a92: 2b00 cmp r3, #0
8003a94: d115 bne.n 8003ac2 <USB_SetCurrentMode+0x80>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
8003a96: 687b ldr r3, [r7, #4]
8003a98: 68db ldr r3, [r3, #12]
8003a9a: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
8003a9e: 687b ldr r3, [r7, #4]
8003aa0: 60da str r2, [r3, #12]
do
{
HAL_Delay(10U);
8003aa2: 200a movs r0, #10
8003aa4: f7fd f9c6 bl 8000e34 <HAL_Delay>
ms += 10U;
8003aa8: 68fb ldr r3, [r7, #12]
8003aaa: 330a adds r3, #10
8003aac: 60fb str r3, [r7, #12]
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
8003aae: 6878 ldr r0, [r7, #4]
8003ab0: f000 fa0c bl 8003ecc <USB_GetMode>
8003ab4: 4603 mov r3, r0
8003ab6: 2b00 cmp r3, #0
8003ab8: d005 beq.n 8003ac6 <USB_SetCurrentMode+0x84>
8003aba: 68fb ldr r3, [r7, #12]
8003abc: 2bc7 cmp r3, #199 @ 0xc7
8003abe: d9f0 bls.n 8003aa2 <USB_SetCurrentMode+0x60>
8003ac0: e001 b.n 8003ac6 <USB_SetCurrentMode+0x84>
}
else
{
return HAL_ERROR;
8003ac2: 2301 movs r3, #1
8003ac4: e005 b.n 8003ad2 <USB_SetCurrentMode+0x90>
}
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
8003ac6: 68fb ldr r3, [r7, #12]
8003ac8: 2bc8 cmp r3, #200 @ 0xc8
8003aca: d101 bne.n 8003ad0 <USB_SetCurrentMode+0x8e>
{
return HAL_ERROR;
8003acc: 2301 movs r3, #1
8003ace: e000 b.n 8003ad2 <USB_SetCurrentMode+0x90>
}
return HAL_OK;
8003ad0: 2300 movs r3, #0
}
8003ad2: 4618 mov r0, r3
8003ad4: 3710 adds r7, #16
8003ad6: 46bd mov sp, r7
8003ad8: bd80 pop {r7, pc}
...
08003adc <USB_DevInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
8003adc: b084 sub sp, #16
8003ade: b580 push {r7, lr}
8003ae0: b086 sub sp, #24
8003ae2: af00 add r7, sp, #0
8003ae4: 6078 str r0, [r7, #4]
8003ae6: f107 0024 add.w r0, r7, #36 @ 0x24
8003aea: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret = HAL_OK;
8003aee: 2300 movs r3, #0
8003af0: 75fb strb r3, [r7, #23]
uint32_t USBx_BASE = (uint32_t)USBx;
8003af2: 687b ldr r3, [r7, #4]
8003af4: 60fb str r3, [r7, #12]
uint32_t i;
for (i = 0U; i < 15U; i++)
8003af6: 2300 movs r3, #0
8003af8: 613b str r3, [r7, #16]
8003afa: e009 b.n 8003b10 <USB_DevInit+0x34>
{
USBx->DIEPTXF[i] = 0U;
8003afc: 687a ldr r2, [r7, #4]
8003afe: 693b ldr r3, [r7, #16]
8003b00: 3340 adds r3, #64 @ 0x40
8003b02: 009b lsls r3, r3, #2
8003b04: 4413 add r3, r2
8003b06: 2200 movs r2, #0
8003b08: 605a str r2, [r3, #4]
for (i = 0U; i < 15U; i++)
8003b0a: 693b ldr r3, [r7, #16]
8003b0c: 3301 adds r3, #1
8003b0e: 613b str r3, [r7, #16]
8003b10: 693b ldr r3, [r7, #16]
8003b12: 2b0e cmp r3, #14
8003b14: d9f2 bls.n 8003afc <USB_DevInit+0x20>
}
/* VBUS Sensing setup */
if (cfg.vbus_sensing_enable == 0U)
8003b16: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8003b1a: 2b00 cmp r3, #0
8003b1c: d11c bne.n 8003b58 <USB_DevInit+0x7c>
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8003b1e: 68fb ldr r3, [r7, #12]
8003b20: f503 6300 add.w r3, r3, #2048 @ 0x800
8003b24: 685b ldr r3, [r3, #4]
8003b26: 68fa ldr r2, [r7, #12]
8003b28: f502 6200 add.w r2, r2, #2048 @ 0x800
8003b2c: f043 0302 orr.w r3, r3, #2
8003b30: 6053 str r3, [r2, #4]
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
8003b32: 687b ldr r3, [r7, #4]
8003b34: 6b9b ldr r3, [r3, #56] @ 0x38
8003b36: f423 1200 bic.w r2, r3, #2097152 @ 0x200000
8003b3a: 687b ldr r3, [r7, #4]
8003b3c: 639a str r2, [r3, #56] @ 0x38
/* B-peripheral session valid override enable */
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
8003b3e: 687b ldr r3, [r7, #4]
8003b40: 681b ldr r3, [r3, #0]
8003b42: f043 0240 orr.w r2, r3, #64 @ 0x40
8003b46: 687b ldr r3, [r7, #4]
8003b48: 601a str r2, [r3, #0]
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
8003b4a: 687b ldr r3, [r7, #4]
8003b4c: 681b ldr r3, [r3, #0]
8003b4e: f043 0280 orr.w r2, r3, #128 @ 0x80
8003b52: 687b ldr r3, [r7, #4]
8003b54: 601a str r2, [r3, #0]
8003b56: e005 b.n 8003b64 <USB_DevInit+0x88>
}
else
{
/* Enable HW VBUS sensing */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
8003b58: 687b ldr r3, [r7, #4]
8003b5a: 6b9b ldr r3, [r3, #56] @ 0x38
8003b5c: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
8003b60: 687b ldr r3, [r7, #4]
8003b62: 639a str r2, [r3, #56] @ 0x38
}
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
8003b64: 68fb ldr r3, [r7, #12]
8003b66: f503 6360 add.w r3, r3, #3584 @ 0xe00
8003b6a: 461a mov r2, r3
8003b6c: 2300 movs r3, #0
8003b6e: 6013 str r3, [r2, #0]
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
8003b70: f897 3029 ldrb.w r3, [r7, #41] @ 0x29
8003b74: 2b01 cmp r3, #1
8003b76: d10d bne.n 8003b94 <USB_DevInit+0xb8>
{
if (cfg.speed == USBD_HS_SPEED)
8003b78: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
8003b7c: 2b00 cmp r3, #0
8003b7e: d104 bne.n 8003b8a <USB_DevInit+0xae>
{
/* Set Core speed to High speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);
8003b80: 2100 movs r1, #0
8003b82: 6878 ldr r0, [r7, #4]
8003b84: f000 f968 bl 8003e58 <USB_SetDevSpeed>
8003b88: e008 b.n 8003b9c <USB_DevInit+0xc0>
}
else
{
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);
8003b8a: 2101 movs r1, #1
8003b8c: 6878 ldr r0, [r7, #4]
8003b8e: f000 f963 bl 8003e58 <USB_SetDevSpeed>
8003b92: e003 b.n 8003b9c <USB_DevInit+0xc0>
#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) ||
defined(STM32F732xx) || defined(STM32F733xx) */
else
{
/* Set Core speed to Full speed mode */
(void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);
8003b94: 2103 movs r1, #3
8003b96: 6878 ldr r0, [r7, #4]
8003b98: f000 f95e bl 8003e58 <USB_SetDevSpeed>
}
/* Flush the FIFOs */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
8003b9c: 2110 movs r1, #16
8003b9e: 6878 ldr r0, [r7, #4]
8003ba0: f000 f8fa bl 8003d98 <USB_FlushTxFifo>
8003ba4: 4603 mov r3, r0
8003ba6: 2b00 cmp r3, #0
8003ba8: d001 beq.n 8003bae <USB_DevInit+0xd2>
{
ret = HAL_ERROR;
8003baa: 2301 movs r3, #1
8003bac: 75fb strb r3, [r7, #23]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
8003bae: 6878 ldr r0, [r7, #4]
8003bb0: f000 f924 bl 8003dfc <USB_FlushRxFifo>
8003bb4: 4603 mov r3, r0
8003bb6: 2b00 cmp r3, #0
8003bb8: d001 beq.n 8003bbe <USB_DevInit+0xe2>
{
ret = HAL_ERROR;
8003bba: 2301 movs r3, #1
8003bbc: 75fb strb r3, [r7, #23]
}
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0U;
8003bbe: 68fb ldr r3, [r7, #12]
8003bc0: f503 6300 add.w r3, r3, #2048 @ 0x800
8003bc4: 461a mov r2, r3
8003bc6: 2300 movs r3, #0
8003bc8: 6113 str r3, [r2, #16]
USBx_DEVICE->DOEPMSK = 0U;
8003bca: 68fb ldr r3, [r7, #12]
8003bcc: f503 6300 add.w r3, r3, #2048 @ 0x800
8003bd0: 461a mov r2, r3
8003bd2: 2300 movs r3, #0
8003bd4: 6153 str r3, [r2, #20]
USBx_DEVICE->DAINTMSK = 0U;
8003bd6: 68fb ldr r3, [r7, #12]
8003bd8: f503 6300 add.w r3, r3, #2048 @ 0x800
8003bdc: 461a mov r2, r3
8003bde: 2300 movs r3, #0
8003be0: 61d3 str r3, [r2, #28]
for (i = 0U; i < cfg.dev_endpoints; i++)
8003be2: 2300 movs r3, #0
8003be4: 613b str r3, [r7, #16]
8003be6: e043 b.n 8003c70 <USB_DevInit+0x194>
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
8003be8: 693b ldr r3, [r7, #16]
8003bea: 015a lsls r2, r3, #5
8003bec: 68fb ldr r3, [r7, #12]
8003bee: 4413 add r3, r2
8003bf0: f503 6310 add.w r3, r3, #2304 @ 0x900
8003bf4: 681b ldr r3, [r3, #0]
8003bf6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8003bfa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8003bfe: d118 bne.n 8003c32 <USB_DevInit+0x156>
{
if (i == 0U)
8003c00: 693b ldr r3, [r7, #16]
8003c02: 2b00 cmp r3, #0
8003c04: d10a bne.n 8003c1c <USB_DevInit+0x140>
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
8003c06: 693b ldr r3, [r7, #16]
8003c08: 015a lsls r2, r3, #5
8003c0a: 68fb ldr r3, [r7, #12]
8003c0c: 4413 add r3, r2
8003c0e: f503 6310 add.w r3, r3, #2304 @ 0x900
8003c12: 461a mov r2, r3
8003c14: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8003c18: 6013 str r3, [r2, #0]
8003c1a: e013 b.n 8003c44 <USB_DevInit+0x168>
}
else
{
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
8003c1c: 693b ldr r3, [r7, #16]
8003c1e: 015a lsls r2, r3, #5
8003c20: 68fb ldr r3, [r7, #12]
8003c22: 4413 add r3, r2
8003c24: f503 6310 add.w r3, r3, #2304 @ 0x900
8003c28: 461a mov r2, r3
8003c2a: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8003c2e: 6013 str r3, [r2, #0]
8003c30: e008 b.n 8003c44 <USB_DevInit+0x168>
}
}
else
{
USBx_INEP(i)->DIEPCTL = 0U;
8003c32: 693b ldr r3, [r7, #16]
8003c34: 015a lsls r2, r3, #5
8003c36: 68fb ldr r3, [r7, #12]
8003c38: 4413 add r3, r2
8003c3a: f503 6310 add.w r3, r3, #2304 @ 0x900
8003c3e: 461a mov r2, r3
8003c40: 2300 movs r3, #0
8003c42: 6013 str r3, [r2, #0]
}
USBx_INEP(i)->DIEPTSIZ = 0U;
8003c44: 693b ldr r3, [r7, #16]
8003c46: 015a lsls r2, r3, #5
8003c48: 68fb ldr r3, [r7, #12]
8003c4a: 4413 add r3, r2
8003c4c: f503 6310 add.w r3, r3, #2304 @ 0x900
8003c50: 461a mov r2, r3
8003c52: 2300 movs r3, #0
8003c54: 6113 str r3, [r2, #16]
USBx_INEP(i)->DIEPINT = 0xFB7FU;
8003c56: 693b ldr r3, [r7, #16]
8003c58: 015a lsls r2, r3, #5
8003c5a: 68fb ldr r3, [r7, #12]
8003c5c: 4413 add r3, r2
8003c5e: f503 6310 add.w r3, r3, #2304 @ 0x900
8003c62: 461a mov r2, r3
8003c64: f64f 337f movw r3, #64383 @ 0xfb7f
8003c68: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
8003c6a: 693b ldr r3, [r7, #16]
8003c6c: 3301 adds r3, #1
8003c6e: 613b str r3, [r7, #16]
8003c70: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003c74: 461a mov r2, r3
8003c76: 693b ldr r3, [r7, #16]
8003c78: 4293 cmp r3, r2
8003c7a: d3b5 bcc.n 8003be8 <USB_DevInit+0x10c>
}
for (i = 0U; i < cfg.dev_endpoints; i++)
8003c7c: 2300 movs r3, #0
8003c7e: 613b str r3, [r7, #16]
8003c80: e043 b.n 8003d0a <USB_DevInit+0x22e>
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
8003c82: 693b ldr r3, [r7, #16]
8003c84: 015a lsls r2, r3, #5
8003c86: 68fb ldr r3, [r7, #12]
8003c88: 4413 add r3, r2
8003c8a: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003c8e: 681b ldr r3, [r3, #0]
8003c90: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8003c94: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8003c98: d118 bne.n 8003ccc <USB_DevInit+0x1f0>
{
if (i == 0U)
8003c9a: 693b ldr r3, [r7, #16]
8003c9c: 2b00 cmp r3, #0
8003c9e: d10a bne.n 8003cb6 <USB_DevInit+0x1da>
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
8003ca0: 693b ldr r3, [r7, #16]
8003ca2: 015a lsls r2, r3, #5
8003ca4: 68fb ldr r3, [r7, #12]
8003ca6: 4413 add r3, r2
8003ca8: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003cac: 461a mov r2, r3
8003cae: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8003cb2: 6013 str r3, [r2, #0]
8003cb4: e013 b.n 8003cde <USB_DevInit+0x202>
}
else
{
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
8003cb6: 693b ldr r3, [r7, #16]
8003cb8: 015a lsls r2, r3, #5
8003cba: 68fb ldr r3, [r7, #12]
8003cbc: 4413 add r3, r2
8003cbe: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003cc2: 461a mov r2, r3
8003cc4: f04f 4390 mov.w r3, #1207959552 @ 0x48000000
8003cc8: 6013 str r3, [r2, #0]
8003cca: e008 b.n 8003cde <USB_DevInit+0x202>
}
}
else
{
USBx_OUTEP(i)->DOEPCTL = 0U;
8003ccc: 693b ldr r3, [r7, #16]
8003cce: 015a lsls r2, r3, #5
8003cd0: 68fb ldr r3, [r7, #12]
8003cd2: 4413 add r3, r2
8003cd4: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003cd8: 461a mov r2, r3
8003cda: 2300 movs r3, #0
8003cdc: 6013 str r3, [r2, #0]
}
USBx_OUTEP(i)->DOEPTSIZ = 0U;
8003cde: 693b ldr r3, [r7, #16]
8003ce0: 015a lsls r2, r3, #5
8003ce2: 68fb ldr r3, [r7, #12]
8003ce4: 4413 add r3, r2
8003ce6: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003cea: 461a mov r2, r3
8003cec: 2300 movs r3, #0
8003cee: 6113 str r3, [r2, #16]
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
8003cf0: 693b ldr r3, [r7, #16]
8003cf2: 015a lsls r2, r3, #5
8003cf4: 68fb ldr r3, [r7, #12]
8003cf6: 4413 add r3, r2
8003cf8: f503 6330 add.w r3, r3, #2816 @ 0xb00
8003cfc: 461a mov r2, r3
8003cfe: f64f 337f movw r3, #64383 @ 0xfb7f
8003d02: 6093 str r3, [r2, #8]
for (i = 0U; i < cfg.dev_endpoints; i++)
8003d04: 693b ldr r3, [r7, #16]
8003d06: 3301 adds r3, #1
8003d08: 613b str r3, [r7, #16]
8003d0a: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
8003d0e: 461a mov r2, r3
8003d10: 693b ldr r3, [r7, #16]
8003d12: 4293 cmp r3, r2
8003d14: d3b5 bcc.n 8003c82 <USB_DevInit+0x1a6>
}
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
8003d16: 68fb ldr r3, [r7, #12]
8003d18: f503 6300 add.w r3, r3, #2048 @ 0x800
8003d1c: 691b ldr r3, [r3, #16]
8003d1e: 68fa ldr r2, [r7, #12]
8003d20: f502 6200 add.w r2, r2, #2048 @ 0x800
8003d24: f423 7380 bic.w r3, r3, #256 @ 0x100
8003d28: 6113 str r3, [r2, #16]
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
8003d2a: 687b ldr r3, [r7, #4]
8003d2c: 2200 movs r2, #0
8003d2e: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFFU;
8003d30: 687b ldr r3, [r7, #4]
8003d32: f06f 4280 mvn.w r2, #1073741824 @ 0x40000000
8003d36: 615a str r2, [r3, #20]
/* Enable the common interrupts */
if (cfg.dma_enable == 0U)
8003d38: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
8003d3c: 2b00 cmp r3, #0
8003d3e: d105 bne.n 8003d4c <USB_DevInit+0x270>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
8003d40: 687b ldr r3, [r7, #4]
8003d42: 699b ldr r3, [r3, #24]
8003d44: f043 0210 orr.w r2, r3, #16
8003d48: 687b ldr r3, [r7, #4]
8003d4a: 619a str r2, [r3, #24]
}
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |
8003d4c: 687b ldr r3, [r7, #4]
8003d4e: 699a ldr r2, [r3, #24]
8003d50: 4b0f ldr r3, [pc, #60] @ (8003d90 <USB_DevInit+0x2b4>)
8003d52: 4313 orrs r3, r2
8003d54: 687a ldr r2, [r7, #4]
8003d56: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM |
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;
if (cfg.Sof_enable != 0U)
8003d58: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
8003d5c: 2b00 cmp r3, #0
8003d5e: d005 beq.n 8003d6c <USB_DevInit+0x290>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
8003d60: 687b ldr r3, [r7, #4]
8003d62: 699b ldr r3, [r3, #24]
8003d64: f043 0208 orr.w r2, r3, #8
8003d68: 687b ldr r3, [r7, #4]
8003d6a: 619a str r2, [r3, #24]
}
if (cfg.vbus_sensing_enable == 1U)
8003d6c: f897 302e ldrb.w r3, [r7, #46] @ 0x2e
8003d70: 2b01 cmp r3, #1
8003d72: d105 bne.n 8003d80 <USB_DevInit+0x2a4>
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
8003d74: 687b ldr r3, [r7, #4]
8003d76: 699a ldr r2, [r3, #24]
8003d78: 4b06 ldr r3, [pc, #24] @ (8003d94 <USB_DevInit+0x2b8>)
8003d7a: 4313 orrs r3, r2
8003d7c: 687a ldr r2, [r7, #4]
8003d7e: 6193 str r3, [r2, #24]
}
return ret;
8003d80: 7dfb ldrb r3, [r7, #23]
}
8003d82: 4618 mov r0, r3
8003d84: 3718 adds r7, #24
8003d86: 46bd mov sp, r7
8003d88: e8bd 4080 ldmia.w sp!, {r7, lr}
8003d8c: b004 add sp, #16
8003d8e: 4770 bx lr
8003d90: 803c3800 .word 0x803c3800
8003d94: 40000004 .word 0x40000004
08003d98 <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
8003d98: b480 push {r7}
8003d9a: b085 sub sp, #20
8003d9c: af00 add r7, sp, #0
8003d9e: 6078 str r0, [r7, #4]
8003da0: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
8003da2: 2300 movs r3, #0
8003da4: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8003da6: 68fb ldr r3, [r7, #12]
8003da8: 3301 adds r3, #1
8003daa: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003dac: 68fb ldr r3, [r7, #12]
8003dae: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003db2: d901 bls.n 8003db8 <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
8003db4: 2303 movs r3, #3
8003db6: e01b b.n 8003df0 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8003db8: 687b ldr r3, [r7, #4]
8003dba: 691b ldr r3, [r3, #16]
8003dbc: 2b00 cmp r3, #0
8003dbe: daf2 bge.n 8003da6 <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
8003dc0: 2300 movs r3, #0
8003dc2: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
8003dc4: 683b ldr r3, [r7, #0]
8003dc6: 019b lsls r3, r3, #6
8003dc8: f043 0220 orr.w r2, r3, #32
8003dcc: 687b ldr r3, [r7, #4]
8003dce: 611a str r2, [r3, #16]
do
{
count++;
8003dd0: 68fb ldr r3, [r7, #12]
8003dd2: 3301 adds r3, #1
8003dd4: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003dd6: 68fb ldr r3, [r7, #12]
8003dd8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003ddc: d901 bls.n 8003de2 <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
8003dde: 2303 movs r3, #3
8003de0: e006 b.n 8003df0 <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
8003de2: 687b ldr r3, [r7, #4]
8003de4: 691b ldr r3, [r3, #16]
8003de6: f003 0320 and.w r3, r3, #32
8003dea: 2b20 cmp r3, #32
8003dec: d0f0 beq.n 8003dd0 <USB_FlushTxFifo+0x38>
return HAL_OK;
8003dee: 2300 movs r3, #0
}
8003df0: 4618 mov r0, r3
8003df2: 3714 adds r7, #20
8003df4: 46bd mov sp, r7
8003df6: f85d 7b04 ldr.w r7, [sp], #4
8003dfa: 4770 bx lr
08003dfc <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
8003dfc: b480 push {r7}
8003dfe: b085 sub sp, #20
8003e00: af00 add r7, sp, #0
8003e02: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8003e04: 2300 movs r3, #0
8003e06: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8003e08: 68fb ldr r3, [r7, #12]
8003e0a: 3301 adds r3, #1
8003e0c: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003e0e: 68fb ldr r3, [r7, #12]
8003e10: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003e14: d901 bls.n 8003e1a <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
8003e16: 2303 movs r3, #3
8003e18: e018 b.n 8003e4c <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8003e1a: 687b ldr r3, [r7, #4]
8003e1c: 691b ldr r3, [r3, #16]
8003e1e: 2b00 cmp r3, #0
8003e20: daf2 bge.n 8003e08 <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
8003e22: 2300 movs r3, #0
8003e24: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
8003e26: 687b ldr r3, [r7, #4]
8003e28: 2210 movs r2, #16
8003e2a: 611a str r2, [r3, #16]
do
{
count++;
8003e2c: 68fb ldr r3, [r7, #12]
8003e2e: 3301 adds r3, #1
8003e30: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003e32: 68fb ldr r3, [r7, #12]
8003e34: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003e38: d901 bls.n 8003e3e <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
8003e3a: 2303 movs r3, #3
8003e3c: e006 b.n 8003e4c <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
8003e3e: 687b ldr r3, [r7, #4]
8003e40: 691b ldr r3, [r3, #16]
8003e42: f003 0310 and.w r3, r3, #16
8003e46: 2b10 cmp r3, #16
8003e48: d0f0 beq.n 8003e2c <USB_FlushRxFifo+0x30>
return HAL_OK;
8003e4a: 2300 movs r3, #0
}
8003e4c: 4618 mov r0, r3
8003e4e: 3714 adds r7, #20
8003e50: 46bd mov sp, r7
8003e52: f85d 7b04 ldr.w r7, [sp], #4
8003e56: 4770 bx lr
08003e58 <USB_SetDevSpeed>:
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
8003e58: b480 push {r7}
8003e5a: b085 sub sp, #20
8003e5c: af00 add r7, sp, #0
8003e5e: 6078 str r0, [r7, #4]
8003e60: 460b mov r3, r1
8003e62: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8003e64: 687b ldr r3, [r7, #4]
8003e66: 60fb str r3, [r7, #12]
USBx_DEVICE->DCFG |= speed;
8003e68: 68fb ldr r3, [r7, #12]
8003e6a: f503 6300 add.w r3, r3, #2048 @ 0x800
8003e6e: 681a ldr r2, [r3, #0]
8003e70: 78fb ldrb r3, [r7, #3]
8003e72: 68f9 ldr r1, [r7, #12]
8003e74: f501 6100 add.w r1, r1, #2048 @ 0x800
8003e78: 4313 orrs r3, r2
8003e7a: 600b str r3, [r1, #0]
return HAL_OK;
8003e7c: 2300 movs r3, #0
}
8003e7e: 4618 mov r0, r3
8003e80: 3714 adds r7, #20
8003e82: 46bd mov sp, r7
8003e84: f85d 7b04 ldr.w r7, [sp], #4
8003e88: 4770 bx lr
08003e8a <USB_DevDisconnect>:
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
8003e8a: b480 push {r7}
8003e8c: b085 sub sp, #20
8003e8e: af00 add r7, sp, #0
8003e90: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
8003e92: 687b ldr r3, [r7, #4]
8003e94: 60fb str r3, [r7, #12]
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
8003e96: 68fb ldr r3, [r7, #12]
8003e98: f503 6360 add.w r3, r3, #3584 @ 0xe00
8003e9c: 681b ldr r3, [r3, #0]
8003e9e: 68fa ldr r2, [r7, #12]
8003ea0: f502 6260 add.w r2, r2, #3584 @ 0xe00
8003ea4: f023 0303 bic.w r3, r3, #3
8003ea8: 6013 str r3, [r2, #0]
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
8003eaa: 68fb ldr r3, [r7, #12]
8003eac: f503 6300 add.w r3, r3, #2048 @ 0x800
8003eb0: 685b ldr r3, [r3, #4]
8003eb2: 68fa ldr r2, [r7, #12]
8003eb4: f502 6200 add.w r2, r2, #2048 @ 0x800
8003eb8: f043 0302 orr.w r3, r3, #2
8003ebc: 6053 str r3, [r2, #4]
return HAL_OK;
8003ebe: 2300 movs r3, #0
}
8003ec0: 4618 mov r0, r3
8003ec2: 3714 adds r7, #20
8003ec4: 46bd mov sp, r7
8003ec6: f85d 7b04 ldr.w r7, [sp], #4
8003eca: 4770 bx lr
08003ecc <USB_GetMode>:
* This parameter can be one of these values:
* 1 : Host
* 0 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
8003ecc: b480 push {r7}
8003ece: b083 sub sp, #12
8003ed0: af00 add r7, sp, #0
8003ed2: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 695b ldr r3, [r3, #20]
8003ed8: f003 0301 and.w r3, r3, #1
}
8003edc: 4618 mov r0, r3
8003ede: 370c adds r7, #12
8003ee0: 46bd mov sp, r7
8003ee2: f85d 7b04 ldr.w r7, [sp], #4
8003ee6: 4770 bx lr
08003ee8 <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
8003ee8: b480 push {r7}
8003eea: b085 sub sp, #20
8003eec: af00 add r7, sp, #0
8003eee: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8003ef0: 2300 movs r3, #0
8003ef2: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8003ef4: 68fb ldr r3, [r7, #12]
8003ef6: 3301 adds r3, #1
8003ef8: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003efa: 68fb ldr r3, [r7, #12]
8003efc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003f00: d901 bls.n 8003f06 <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
8003f02: 2303 movs r3, #3
8003f04: e022 b.n 8003f4c <USB_CoreReset+0x64>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8003f06: 687b ldr r3, [r7, #4]
8003f08: 691b ldr r3, [r3, #16]
8003f0a: 2b00 cmp r3, #0
8003f0c: daf2 bge.n 8003ef4 <USB_CoreReset+0xc>
count = 10U;
8003f0e: 230a movs r3, #10
8003f10: 60fb str r3, [r7, #12]
/* few cycles before setting core reset */
while (count > 0U)
8003f12: e002 b.n 8003f1a <USB_CoreReset+0x32>
{
count--;
8003f14: 68fb ldr r3, [r7, #12]
8003f16: 3b01 subs r3, #1
8003f18: 60fb str r3, [r7, #12]
while (count > 0U)
8003f1a: 68fb ldr r3, [r7, #12]
8003f1c: 2b00 cmp r3, #0
8003f1e: d1f9 bne.n 8003f14 <USB_CoreReset+0x2c>
}
/* Core Soft Reset */
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
8003f20: 687b ldr r3, [r7, #4]
8003f22: 691b ldr r3, [r3, #16]
8003f24: f043 0201 orr.w r2, r3, #1
8003f28: 687b ldr r3, [r7, #4]
8003f2a: 611a str r2, [r3, #16]
do
{
count++;
8003f2c: 68fb ldr r3, [r7, #12]
8003f2e: 3301 adds r3, #1
8003f30: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8003f32: 68fb ldr r3, [r7, #12]
8003f34: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8003f38: d901 bls.n 8003f3e <USB_CoreReset+0x56>
{
return HAL_TIMEOUT;
8003f3a: 2303 movs r3, #3
8003f3c: e006 b.n 8003f4c <USB_CoreReset+0x64>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
8003f3e: 687b ldr r3, [r7, #4]
8003f40: 691b ldr r3, [r3, #16]
8003f42: f003 0301 and.w r3, r3, #1
8003f46: 2b01 cmp r3, #1
8003f48: d0f0 beq.n 8003f2c <USB_CoreReset+0x44>
return HAL_OK;
8003f4a: 2300 movs r3, #0
}
8003f4c: 4618 mov r0, r3
8003f4e: 3714 adds r7, #20
8003f50: 46bd mov sp, r7
8003f52: f85d 7b04 ldr.w r7, [sp], #4
8003f56: 4770 bx lr
08003f58 <memset>:
8003f58: 4402 add r2, r0
8003f5a: 4603 mov r3, r0
8003f5c: 4293 cmp r3, r2
8003f5e: d100 bne.n 8003f62 <memset+0xa>
8003f60: 4770 bx lr
8003f62: f803 1b01 strb.w r1, [r3], #1
8003f66: e7f9 b.n 8003f5c <memset+0x4>
08003f68 <__libc_init_array>:
8003f68: b570 push {r4, r5, r6, lr}
8003f6a: 4d0d ldr r5, [pc, #52] @ (8003fa0 <__libc_init_array+0x38>)
8003f6c: 4c0d ldr r4, [pc, #52] @ (8003fa4 <__libc_init_array+0x3c>)
8003f6e: 1b64 subs r4, r4, r5
8003f70: 10a4 asrs r4, r4, #2
8003f72: 2600 movs r6, #0
8003f74: 42a6 cmp r6, r4
8003f76: d109 bne.n 8003f8c <__libc_init_array+0x24>
8003f78: 4d0b ldr r5, [pc, #44] @ (8003fa8 <__libc_init_array+0x40>)
8003f7a: 4c0c ldr r4, [pc, #48] @ (8003fac <__libc_init_array+0x44>)
8003f7c: f000 f818 bl 8003fb0 <_init>
8003f80: 1b64 subs r4, r4, r5
8003f82: 10a4 asrs r4, r4, #2
8003f84: 2600 movs r6, #0
8003f86: 42a6 cmp r6, r4
8003f88: d105 bne.n 8003f96 <__libc_init_array+0x2e>
8003f8a: bd70 pop {r4, r5, r6, pc}
8003f8c: f855 3b04 ldr.w r3, [r5], #4
8003f90: 4798 blx r3
8003f92: 3601 adds r6, #1
8003f94: e7ee b.n 8003f74 <__libc_init_array+0xc>
8003f96: f855 3b04 ldr.w r3, [r5], #4
8003f9a: 4798 blx r3
8003f9c: 3601 adds r6, #1
8003f9e: e7f2 b.n 8003f86 <__libc_init_array+0x1e>
8003fa0: 08003fe8 .word 0x08003fe8
8003fa4: 08003fe8 .word 0x08003fe8
8003fa8: 08003fe8 .word 0x08003fe8
8003fac: 08003fec .word 0x08003fec
08003fb0 <_init>:
8003fb0: b5f8 push {r3, r4, r5, r6, r7, lr}
8003fb2: bf00 nop
8003fb4: bcf8 pop {r3, r4, r5, r6, r7}
8003fb6: bc08 pop {r3}
8003fb8: 469e mov lr, r3
8003fba: 4770 bx lr
08003fbc <_fini>:
8003fbc: b5f8 push {r3, r4, r5, r6, r7, lr}
8003fbe: bf00 nop
8003fc0: bcf8 pop {r3, r4, r5, r6, r7}
8003fc2: bc08 pop {r3}
8003fc4: 469e mov lr, r3
8003fc6: 4770 bx lr
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