From fcf154c07d13bb2f80196d0381d2f3c85eb84b63 Mon Sep 17 00:00:00 2001
From: Lyubomir Penev <me@lpenev.com>
Date: Wed, 12 Nov 2025 22:00:07 +0100
Subject: [PATCH] Set pin modes

---
 .cproject                                     |    2 +-
 .mxproject                                    |   16 +-
 .settings/stm32cubeide.project.prefs          |    2 +-
 Core/Inc/main.h                               |   12 +-
 Core/Inc/stm32f7xx_hal_conf.h                 |    4 +-
 Core/Src/main.c                               |  132 +-
 Core/Src/stm32f7xx_hal_msp.c                  |  110 -
 .../Inc/stm32f7xx_hal_eth.h                   | 2017 ----------
 .../Src/stm32f7xx_hal_eth.c                   | 3308 -----------------
 Volume-Controller-STM.ioc                     |  107 +-
 10 files changed, 138 insertions(+), 5572 deletions(-)
 delete mode 100644 Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h
 delete mode 100644 Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c

diff --git a/.cproject b/.cproject
index c30f88e..1796d23 100644
--- a/.cproject
+++ b/.cproject
@@ -117,7 +117,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1265647422" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1844694981" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-F767ZI" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1221902238" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || NUCLEO-F767ZI || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32F7xx_HAL_Driver/Inc | ../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32F7xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32F767xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32F767ZITX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.56027543" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="96" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.56027543" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="96" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.591389149" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/Volume-Controller-STM}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.148248156" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.173764429" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/.mxproject b/.mxproject
index b03f2c3..1c30176 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,3 +1,11 @@
+[PreviousLibFiles]
+LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f767xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\stm32f7xx_it.c;Core\Src\stm32f7xx_hal_msp.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Core\Src\system_stm32f7xx.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Core\Src\system_stm32f7xx.c;;;
+HeaderPath=Drivers\STM32F7xx_HAL_Driver\Inc;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F7xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
 [PreviousGenFiles]
 AdvancedFolderStructure=true
 HeaderFileListSize=3
@@ -15,11 +23,3 @@ SourceFolderListSize=1
 SourcePath#0=..\Core\Src
 SourceFiles=;
 
-[PreviousLibFiles]
-LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pcd_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usb.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f767xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
-
-[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32f7xx_it.c;Core\Src\stm32f7xx_hal_msp.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Core\Src\system_stm32f7xx.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pcd_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c;Core\Src\system_stm32f7xx.c;;;
-HeaderPath=Drivers\STM32F7xx_HAL_Driver\Inc;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F7xx\Include;Drivers\CMSIS\Include;Core\Inc;
-CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
-
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
index 6874a84..cb52da3 100644
--- a/.settings/stm32cubeide.project.prefs
+++ b/.settings/stm32cubeide.project.prefs
@@ -1,5 +1,5 @@
 635E684B79701B039C64EA45C3F84D30=47742E4A030C555085AC15FBAAE1D09F
-66BE74F758C12D739921AEA421D593D3=0
+66BE74F758C12D739921AEA421D593D3=1
 8DF89ED150041C4CBC7CB9A9CAA90856=B48C61BDAF788954EA511914FEFE7267
 DC22A860405A8BF2F2C095E5B6529F12=B48C61BDAF788954EA511914FEFE7267
 eclipse.preferences.version=1
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 34d71a4..06b951b 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -59,6 +59,8 @@ void Error_Handler(void);
 /* Private defines -----------------------------------------------------------*/
 #define USER_Btn_Pin GPIO_PIN_13
 #define USER_Btn_GPIO_Port GPIOC
+#define Pot_CS_Pin GPIO_PIN_2
+#define Pot_CS_GPIO_Port GPIOF
 #define MCO_Pin GPIO_PIN_0
 #define MCO_GPIO_Port GPIOH
 #define RMII_MDC_Pin GPIO_PIN_1
@@ -67,14 +69,20 @@ void Error_Handler(void);
 #define RMII_REF_CLK_GPIO_Port GPIOA
 #define RMII_MDIO_Pin GPIO_PIN_2
 #define RMII_MDIO_GPIO_Port GPIOA
-#define RMII_CRS_DV_Pin GPIO_PIN_7
-#define RMII_CRS_DV_GPIO_Port GPIOA
+#define Pot_UD_Pin GPIO_PIN_7
+#define Pot_UD_GPIO_Port GPIOA
 #define RMII_RXD0_Pin GPIO_PIN_4
 #define RMII_RXD0_GPIO_Port GPIOC
 #define RMII_RXD1_Pin GPIO_PIN_5
 #define RMII_RXD1_GPIO_Port GPIOC
 #define LD1_Pin GPIO_PIN_0
 #define LD1_GPIO_Port GPIOB
+#define Remote_B_Pin GPIO_PIN_10
+#define Remote_B_GPIO_Port GPIOE
+#define Remote_C_Pin GPIO_PIN_12
+#define Remote_C_GPIO_Port GPIOE
+#define Remote_D_Pin GPIO_PIN_14
+#define Remote_D_GPIO_Port GPIOE
 #define RMII_TXD1_Pin GPIO_PIN_13
 #define RMII_TXD1_GPIO_Port GPIOB
 #define LD3_Pin GPIO_PIN_14
diff --git a/Core/Inc/stm32f7xx_hal_conf.h b/Core/Inc/stm32f7xx_hal_conf.h
index 4dc0ce6..88534b0 100644
--- a/Core/Inc/stm32f7xx_hal_conf.h
+++ b/Core/Inc/stm32f7xx_hal_conf.h
@@ -45,7 +45,7 @@
 /* #define HAL_DAC_MODULE_ENABLED */
 /* #define HAL_DCMI_MODULE_ENABLED */
 /* #define HAL_DMA2D_MODULE_ENABLED */
-#define HAL_ETH_MODULE_ENABLED
+/* #define HAL_ETH_MODULE_ENABLED */
 /* #define HAL_ETH_LEGACY_MODULE_ENABLED */
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
@@ -210,7 +210,7 @@
 #define MAC_ADDR5   0U
 
 /* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                1524 /* buffer size for receive               */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
 #define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 450b6ef..4ce0672 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -18,7 +18,6 @@
 /* USER CODE END Header */
 /* Includes ------------------------------------------------------------------*/
 #include "main.h"
-#include "string.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
@@ -41,26 +40,6 @@
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
-#if defined ( __ICCARM__ ) /*!< IAR Compiler */
-#pragma location=0x2007c000
-ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
-#pragma location=0x2007c0a0
-ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
-
-#elif defined ( __CC_ARM )  /* MDK ARM Compiler */
-
-__attribute__((at(0x2007c000))) ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
-__attribute__((at(0x2007c0a0))) ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
-
-#elif defined ( __GNUC__ ) /* GNU Compiler */
-
-ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
-ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection")));   /* Ethernet Tx DMA Descriptors */
-#endif
-
-ETH_TxPacketConfig TxConfig;
-
-ETH_HandleTypeDef heth;
 
 UART_HandleTypeDef huart3;
 
@@ -73,7 +52,6 @@ PCD_HandleTypeDef hpcd_USB_OTG_FS;
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
-static void MX_ETH_Init(void);
 static void MX_USART3_UART_Init(void);
 static void MX_USB_OTG_FS_PCD_Init(void);
 /* USER CODE BEGIN PFP */
@@ -114,7 +92,6 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
-  MX_ETH_Init();
   MX_USART3_UART_Init();
   MX_USB_OTG_FS_PCD_Init();
   /* USER CODE BEGIN 2 */
@@ -193,55 +170,6 @@ void SystemClock_Config(void)
   }
 }
 
-/**
-  * @brief ETH Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_ETH_Init(void)
-{
-
-  /* USER CODE BEGIN ETH_Init 0 */
-
-  /* USER CODE END ETH_Init 0 */
-
-   static uint8_t MACAddr[6];
-
-  /* USER CODE BEGIN ETH_Init 1 */
-
-  /* USER CODE END ETH_Init 1 */
-  heth.Instance = ETH;
-  MACAddr[0] = 0x00;
-  MACAddr[1] = 0x80;
-  MACAddr[2] = 0xE1;
-  MACAddr[3] = 0x00;
-  MACAddr[4] = 0x00;
-  MACAddr[5] = 0x00;
-  heth.Init.MACAddr = &MACAddr[0];
-  heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
-  heth.Init.TxDesc = DMATxDscrTab;
-  heth.Init.RxDesc = DMARxDscrTab;
-  heth.Init.RxBuffLen = 1524;
-
-  /* USER CODE BEGIN MACADDRESS */
-
-  /* USER CODE END MACADDRESS */
-
-  if (HAL_ETH_Init(&heth) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
-  TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
-  TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
-  TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
-  /* USER CODE BEGIN ETH_Init 2 */
-
-  /* USER CODE END ETH_Init 2 */
-
-}
-
 /**
   * @brief USART3 Initialization Function
   * @param None
@@ -326,12 +254,20 @@ static void MX_GPIO_Init(void)
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOG_CLK_ENABLE();
 
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(Pot_CS_GPIO_Port, Pot_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(Pot_UD_GPIO_Port, Pot_UD_Pin, GPIO_PIN_RESET);
+
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin|LD2_Pin, GPIO_PIN_RESET);
 
@@ -344,6 +280,36 @@ static void MX_GPIO_Init(void)
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct);
 
+  /*Configure GPIO pin : Pot_CS_Pin */
+  GPIO_InitStruct.Pin = Pot_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(Pot_CS_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : RMII_MDC_Pin RMII_RXD0_Pin RMII_RXD1_Pin */
+  GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : RMII_REF_CLK_Pin RMII_MDIO_Pin */
+  GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : Pot_UD_Pin */
+  GPIO_InitStruct.Pin = Pot_UD_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(Pot_UD_GPIO_Port, &GPIO_InitStruct);
+
   /*Configure GPIO pins : LD1_Pin LD3_Pin LD2_Pin */
   GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin|LD2_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -351,6 +317,20 @@ static void MX_GPIO_Init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+  /*Configure GPIO pins : Remote_B_Pin Remote_C_Pin Remote_D_Pin */
+  GPIO_InitStruct.Pin = Remote_B_Pin|Remote_C_Pin|Remote_D_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : RMII_TXD1_Pin */
+  GPIO_InitStruct.Pin = RMII_TXD1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+  HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
+
   /*Configure GPIO pin : USB_PowerSwitchOn_Pin */
   GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -364,6 +344,14 @@ static void MX_GPIO_Init(void)
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
 
+  /*Configure GPIO pins : RMII_TX_EN_Pin RMII_TXD0_Pin */
+  GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
   /* USER CODE BEGIN MX_GPIO_Init_2 */
 
   /* USER CODE END MX_GPIO_Init_2 */
diff --git a/Core/Src/stm32f7xx_hal_msp.c b/Core/Src/stm32f7xx_hal_msp.c
index 592278d..5ba7e07 100644
--- a/Core/Src/stm32f7xx_hal_msp.c
+++ b/Core/Src/stm32f7xx_hal_msp.c
@@ -77,116 +77,6 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
-/**
-  * @brief ETH MSP Initialization
-  * This function configures the hardware resources used in this example
-  * @param heth: ETH handle pointer
-  * @retval None
-  */
-void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(heth->Instance==ETH)
-  {
-    /* USER CODE BEGIN ETH_MspInit 0 */
-
-    /* USER CODE END ETH_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_ETH_CLK_ENABLE();
-
-    __HAL_RCC_GPIOC_CLK_ENABLE();
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    __HAL_RCC_GPIOB_CLK_ENABLE();
-    __HAL_RCC_GPIOG_CLK_ENABLE();
-    /**ETH GPIO Configuration
-    PC1     ------> ETH_MDC
-    PA1     ------> ETH_REF_CLK
-    PA2     ------> ETH_MDIO
-    PA7     ------> ETH_CRS_DV
-    PC4     ------> ETH_RXD0
-    PC5     ------> ETH_RXD1
-    PB13     ------> ETH_TXD1
-    PG11     ------> ETH_TX_EN
-    PG13     ------> ETH_TXD0
-    */
-    GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
-    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = RMII_TXD1_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
-    HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
-    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-
-    /* USER CODE BEGIN ETH_MspInit 1 */
-
-    /* USER CODE END ETH_MspInit 1 */
-
-  }
-
-}
-
-/**
-  * @brief ETH MSP De-Initialization
-  * This function freeze the hardware resources used in this example
-  * @param heth: ETH handle pointer
-  * @retval None
-  */
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
-{
-  if(heth->Instance==ETH)
-  {
-    /* USER CODE BEGIN ETH_MspDeInit 0 */
-
-    /* USER CODE END ETH_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_ETH_CLK_DISABLE();
-
-    /**ETH GPIO Configuration
-    PC1     ------> ETH_MDC
-    PA1     ------> ETH_REF_CLK
-    PA2     ------> ETH_MDIO
-    PA7     ------> ETH_CRS_DV
-    PC4     ------> ETH_RXD0
-    PC5     ------> ETH_RXD1
-    PB13     ------> ETH_TXD1
-    PG11     ------> ETH_TX_EN
-    PG13     ------> ETH_TXD0
-    */
-    HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
-
-    HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
-
-    HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
-
-    HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
-
-    /* USER CODE BEGIN ETH_MspDeInit 1 */
-
-    /* USER CODE END ETH_MspDeInit 1 */
-  }
-
-}
-
 /**
   * @brief UART MSP Initialization
   * This function configures the hardware resources used in this example
diff --git a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h b/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h
deleted file mode 100644
index d7df00d..0000000
--- a/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h
+++ /dev/null
@@ -1,2017 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_eth.h
-  * @author  MCD Application Team
-  * @brief   Header file of ETH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F7xx_HAL_ETH_H
-#define STM32F7xx_HAL_ETH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
-
-#if defined(ETH)
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ETH
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-#ifndef ETH_TX_DESC_CNT
-#define ETH_TX_DESC_CNT         4U
-#endif /* ETH_TX_DESC_CNT */
-
-#ifndef ETH_RX_DESC_CNT
-#define ETH_RX_DESC_CNT         4U
-#endif /* ETH_RX_DESC_CNT */
-
-
-/*********************** Descriptors struct def section ************************/
-/** @defgroup ETH_Exported_Types ETH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  ETH DMA Descriptor structure definition
-  */
-typedef struct
-{
-  __IO uint32_t DESC0;
-  __IO uint32_t DESC1;
-  __IO uint32_t DESC2;
-  __IO uint32_t DESC3;
-  __IO uint32_t DESC4;
-  __IO uint32_t DESC5;
-  __IO uint32_t DESC6;
-  __IO uint32_t DESC7;
-  uint32_t BackupAddr0; /* used to store rx buffer 1 address */
-  uint32_t BackupAddr1; /* used to store rx buffer 2 address */
-} ETH_DMADescTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  ETH Buffers List structure definition
-  */
-typedef struct __ETH_BufferTypeDef
-{
-  uint8_t *buffer;                /*<! buffer address */
-
-  uint32_t len;                   /*<! buffer length */
-
-  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
-} ETH_BufferTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  DMA Transmit Descriptors Wrapper structure definition
-  */
-typedef struct
-{
-  uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
-
-  uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
-
-  uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
-
-  uint32_t *CurrentPacketAddress;           /*<! Current transmit packet addresses */
-
-  uint32_t BuffersInUse;                   /*<! Buffers in Use */
-
-  uint32_t releaseIndex;                  /*<! Release index */
-} ETH_TxDescListTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  Transmit Packet Configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Attributes;              /*!< Tx packet HW features capabilities.
-                                         This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
-
-  uint32_t Length;                  /*!< Total packet length   */
-
-  ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
-
-  uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
-                                         This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
-
-  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
-                                        This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
-
-  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
-                                        This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
-
-  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
-                                        This parameter can be a value from 0x0 to 0x3FFF */
-
-  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
-                                        This parameter can be a value from 0x0 to 0x3FFFF */
-
-  uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
-                                        This parameter can be a value from 0x5 to 0xF */
-
-  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
-                                        This parameter can be a value from 0x0 to 0xFFFF*/
-
-  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
-                                        This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
-
-  uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
-                                        This parameter can be a value from 0x0 to 0x3FFFF */
-
-  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
-                                        This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
-
-  void *pData;                     /*!< Specifies Application packet pointer to save   */
-
-} ETH_TxPacketConfigTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  ETH Timestamp structure definition
-  */
-typedef struct
-{
-  uint32_t TimeStampLow;
-  uint32_t TimeStampHigh;
-
-} ETH_TimeStampTypeDef;
-/**
-  *
-  */
-
-#ifdef HAL_ETH_USE_PTP
-/**
-  * @brief  ETH Timeupdate structure definition
-  */
-typedef struct
-{
-  uint32_t Seconds;
-  uint32_t NanoSeconds;
-} ETH_TimeTypeDef;
-/**
-  *
-  */
-#endif  /* HAL_ETH_USE_PTP */
-
-/**
-  * @brief  DMA Receive Descriptors Wrapper structure definition
-  */
-typedef struct
-{
-  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
-
-  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
-                                             If 0, DMA will not generate the Rx complete interrupt. */
-
-  uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
-
-  uint32_t RxDescCnt;                 /*<! Number of descriptors . */
-
-  uint32_t RxDataLength;              /*<! Received Data Length. */
-
-  uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
-
-  uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
-
-  uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
-
-  ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
-
-  void *pRxStart;                     /*<! Pointer to the first buff. */
-
-  void *pRxEnd;                       /*<! Pointer to the last buff. */
-
-} ETH_RxDescListTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  ETH MAC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t
-  SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
-                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */
-
-  FunctionalState
-  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
-
-  uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
-                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */
-
-  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
-
-  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
-
-  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
-
-  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
-
-  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
-
-  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
-
-  FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
-                                                           When enabled, the MAC allows jumbo packets of 9,018 bytes
-                                                           without reporting a giant packet error */
-
-  uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
-                                                           This parameter can be a value of @ref ETH_Speed */
-
-  uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
-                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
-
-  FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
-
-  FunctionalState
-  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
-
-  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
-
-  FunctionalState
-  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
-
-  FunctionalState
-  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
-
-  uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
-                                                        This parameter can be a value of @ref ETH_Back_Off_Limit */
-
-  FunctionalState
-  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
-
-  uint32_t
-  PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
-                                                           This parameter can be a value of @ref ETH_Preamble_Length */
-
-  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
-
-  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
-
-  uint32_t
-  GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
-                                                    greater than the value programmed in this field in units of bytes
-                                                    This parameter must be a number between
-                                                    Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
-
-  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
-
-  uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
-                                                           This parameter can be a value from 0x0 to 0xFF */
-
-  FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
-
-  uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
-                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */
-
-  uint32_t
-  PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
-                                                   This parameter must be a number between
-                                                   Min_Data = 0x0 and Max_Data = 0xFFFF.*/
-
-  FunctionalState
-  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
-
-  uint32_t
-  PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
-                                                   This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
-  FunctionalState
-  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
-                                                   or the MAC back pressure operation in Half Duplex mode */
-
-  FunctionalState
-  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
-
-  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
-                                                  and disables its transmitter for a specified (Pause) time */
-
-  uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
-                                                      This parameter can be a value of @ref ETH_Transmit_Mode */
-
-  uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
-                                                             This parameter can be a value of @ref ETH_Receive_Mode */
-
-  FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
-
-  FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
-
-  FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
-} ETH_MACConfigTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  ETH DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
-                                                         This parameter can be a value of @ref ETH_DMA_Arbitration */
-
-  FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
-                                                            burst transfers on Read and Write channels  */
-
-  uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
-                                                     This parameter can be a value of @ref ETH_Burst_Mode */
-  FunctionalState      DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */
-
-  FunctionalState      ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode */
-
-  FunctionalState      TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode */
-
-
-  uint32_t
-  TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
-                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-
-  uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
-                                                             This parameter can be a value of
-                                                             @ref ETH_Transmit_Threshold_Control */
-
-  uint32_t
-  RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
-                                                    This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
-
-  FunctionalState      ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames */
-  FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
-
-  FunctionalState
-  ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
-                                                             and length less than 64 bytes)
-                                                             including pad-bytes and CRC) */
-
-  uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
-                                                             This parameter can be a value of
-                                                             @ref ETH_Receive_Threshold_Control */
-
-  FunctionalState
-  SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
-                                                             frame of Transmit data even before obtaining
-                                                             the status for the first frame */
-
-  FunctionalState      EnhancedDescriptorFormat;    /*!< Enables the enhanced descriptor format */
-
-  uint32_t
-  DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
-                                                             This parameter must be a number between
-                                                             Min_Data = 0 and Max_Data = 32 */
-} ETH_DMAConfigTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  HAL ETH Media Interfaces enum definition
-  */
-typedef enum
-{
-  HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
-  HAL_ETH_RMII_MODE            = SYSCFG_PMC_MII_RMII_SEL    /*!<   Reduced Media Independent Interface       */
-} ETH_MediaInterfaceTypeDef;
-/**
-  *
-  */
-
-#ifdef HAL_ETH_USE_PTP
-/**
-  * @brief  HAL ETH PTP Update type enum definition
-  */
-typedef enum
-{
-  HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
-  HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
-} ETH_PtpUpdateTypeDef;
-/**
-  *
-  */
-#endif  /* HAL_ETH_USE_PTP */
-
-/**
-  * @brief  ETH Init Structure definition
-  */
-typedef struct
-{
-  uint8_t
-  *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-
-  ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
-
-  ETH_DMADescTypeDef
-  *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
-
-  ETH_DMADescTypeDef
-  *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
-
-  uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
-
-} ETH_InitTypeDef;
-/**
-  *
-  */
-
-#ifdef HAL_ETH_USE_PTP
-/**
-  * @brief  ETH PTP Init Structure definition
-  */
-typedef struct
-{
-  uint32_t                    Timestamp;                    /*!< Enable Timestamp */
-  uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
-  uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
-  uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
-  uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
-  uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
-  uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
-  uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
-  uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
-  uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
-  uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
-  uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
-  uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
-  uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
-  uint32_t                    TimestampClockType;           /*!< Time stamp clock node type */
-  uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
-  uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
-
-} ETH_PTP_ConfigTypeDef;
-/**
-  *
-  */
-#endif  /* HAL_ETH_USE_PTP */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef uint32_t HAL_ETH_StateTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  HAL ETH Rx Get Buffer Function definition
-  */
-typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
-/**
-  *
-  */
-
-/**
-  * @brief  HAL ETH Rx Set App Data Function definition
-  */
-typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
-                                            uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
-/**
-  *
-  */
-
-/**
-  * @brief  HAL ETH Tx Free Function definition
-  */
-typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
-/**
-  *
-  */
-
-/**
-  * @brief  HAL ETH Tx Free Function definition
-  */
-typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
-                                           ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
-/**
-  *
-  */
-
-/**
-  * @brief  ETH Handle Structure definition
-  */
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-typedef struct __ETH_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-{
-  ETH_TypeDef                *Instance;                 /*!< Register base address       */
-
-  ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
-
-  ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
-                                                            addresses and current descriptor index  */
-
-  ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
-                                                            addresses and current descriptor index  */
-
-#ifdef HAL_ETH_USE_PTP
-  ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
-#endif /* HAL_ETH_USE_PTP */
-
-  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
-                                                              and also related to Tx operations. This parameter can
-                                                              be a value of @ref ETH_State_Codes */
-
-  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
-                                                             This parameter can be a value of @ref ETH_Error_Code.*/
-
-  __IO uint32_t
-  DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
-                                                             This parameter can be a combination of
-                                                             @ref ETH_DMA_Status_Flags */
-
-  __IO uint32_t
-  MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
-                                                             This parameter can be a combination of
-                                                             @ref ETH_MAC_Rx_Tx_Status */
-
-  __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
-                                                             This parameter can be a value of
-                                                             @ref ETH_MAC_Wake_Up_Event */
-
-  __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
-                                                             This parameter can be a value of @ref ETHEx_LPI_Event */
-
-  __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
-                                                             This parameter can be a value of
-                                                             @ref ETH_PTP_Config_Status */
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-
-  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
-  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
-  void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
-  void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
-  void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
-
-  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
-  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
-
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-  pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
-  pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
-  pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
-  pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
-
-} ETH_HandleTypeDef;
-/**
-  *
-  */
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL ETH Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
-  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
-  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
-  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
-  HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
-  HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
-  HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
-
-} HAL_ETH_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL ETH Callback pointer definition
-  */
-typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
-
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
-  * @brief  ETH MAC filter structure definition
-  */
-typedef struct
-{
-  FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
-
-  FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
-
-  FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
-
-  FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
-
-  FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
-
-  FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
-
-  FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
-
-  FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
-
-  FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
-
-  FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
-
-  uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
-                                                 This parameter can be a value of @ref ETH_Control_Packets_Filter */
-} ETH_MACFilterConfigTypeDef;
-/**
-  *
-  */
-
-/**
-  * @brief  ETH Power Down structure definition
-  */
-typedef struct
-{
-  FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
-
-  FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
-
-  FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
-
-  FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
-
-} ETH_PowerDownConfigTypeDef;
-/**
-  *
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ETH_Exported_Constants ETH Exported Constants
-  * @{
-  */
-
-/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
-  * @{
-  */
-
-/*
-   DMA Tx Normal Descriptor Read Format
-  -----------------------------------------------------------------------------------------------
-  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-  -----------------------------------------------------------------------------------------------
-  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
-  -----------------------------------------------------------------------------------------------
-  TDES2 |                         Buffer1 Address [31:0]                                         |
-  -----------------------------------------------------------------------------------------------
-  TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
-  -----------------------------------------------------------------------------------------------
-*/
-
-/**
-  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
-  */
-#define ETH_DMATXDESC_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC                      0x40000000U  /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS                      0x20000000U  /*!< Last Segment */
-#define ETH_DMATXDESC_FS                      0x10000000U  /*!< First Segment */
-#define ETH_DMATXDESC_DC                      0x08000000U  /*!< Disable CRC */
-#define ETH_DMATXDESC_DP                      0x04000000U  /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE                    0x02000000U  /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC                     0x00C00000U  /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS              0x00000000U  /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U  /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER                     0x00200000U  /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH                     0x00100000U  /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS                    0x00020000U  /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE                     0x00010000U  /*!< IP Header Error */
-#define ETH_DMATXDESC_ES                      0x00008000U  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT                      0x00004000U  /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF                      0x00002000U  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE                     0x00001000U  /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF                      0x00000080U  /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC                      0x00000078U  /*!< Collision Count */
-#define ETH_DMATXDESC_ED                      0x00000004U  /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF                      0x00000002U  /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB                      0x00000001U  /*!< Deferred Bit */
-
-/**
-  * @brief  Bit definition of TDES1 register
-  */
-#define ETH_DMATXDESC_TBS2                    0x1FFF0000U  /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1                    0x00001FFFU  /*!< Transmit Buffer1 Size */
-
-/**
-  * @brief  Bit definition of TDES2 register
-  */
-#define ETH_DMATXDESC_B1AP                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
-
-/**
-  * @brief  Bit definition of TDES3 register
-  */
-#define ETH_DMATXDESC_B2AP                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
-
-/*---------------------------------------------------------------------------------------------
-TDES6 |                         Transmit Time Stamp Low [31:0]                                 |
------------------------------------------------------------------------------------------------
-TDES7 |                         Transmit Time Stamp High [31:0]                                |
-----------------------------------------------------------------------------------------------*/
-
-/* Bit definition of TDES6 register */
-#define ETH_DMAPTPTXDESC_TTSL                 0xFFFFFFFFU  /* Transmit Time Stamp Low */
-
-/* Bit definition of TDES7 register */
-#define ETH_DMAPTPTXDESC_TTSH                 0xFFFFFFFFU  /* Transmit Time Stamp High */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
-  * @{
-  */
-
-/*
-  DMA Rx Normal Descriptor read format
-  --------------------------------------------------------------------------------------------------------------------
-  RDES0 | OWN(31) |                                             Status [30:0]                                          |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES2 |                                       Buffer1 Address [31:0]                                                 |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
-  ---------------------------------------------------------------------------------------------------------------------
-*/
-
-/**
-  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
-  */
-#define ETH_DMARXDESC_OWN         0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
-#define ETH_DMARXDESC_AFM         0x40000000U  /*!< DA Filter Fail for the rx frame  */
-#define ETH_DMARXDESC_FL          0x3FFF0000U  /*!< Receive descriptor frame length  */
-#define ETH_DMARXDESC_ES          0x00008000U  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE          0x00004000U  /*!< Descriptor error: no more descriptors for receive frame  */
-#define ETH_DMARXDESC_SAF         0x00002000U  /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE          0x00001000U  /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE          0x00000800U  /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN        0x00000400U  /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS          0x00000200U  /*!< First descriptor of the frame  */
-#define ETH_DMARXDESC_LS          0x00000100U  /*!< Last descriptor of the frame  */
-#define ETH_DMARXDESC_IPV4HCE     0x00000080U  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
-#define ETH_DMARXDESC_LC          0x00000040U  /*!< Late collision occurred during reception   */
-#define ETH_DMARXDESC_FT          0x00000020U  /*!< Frame type - Ethernet, otherwise 802.3    */
-#define ETH_DMARXDESC_RWT         0x00000010U  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
-#define ETH_DMARXDESC_RE          0x00000008U  /*!< Receive error: error reported by MII interface  */
-#define ETH_DMARXDESC_DBE         0x00000004U  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
-#define ETH_DMARXDESC_CE          0x00000002U  /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE      0x00000001U  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/**
-  * @brief  Bit definition of RDES1 register
-  */
-#define ETH_DMARXDESC_DIC         0x80000000U  /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2        0x1FFF0000U  /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER         0x00008000U  /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH         0x00004000U  /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1        0x00001FFFU  /*!< Receive Buffer1 Size */
-
-/**
-  * @brief  Bit definition of RDES2 register
-  */
-#define ETH_DMARXDESC_B1AP        0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
-
-/**
-  * @brief  Bit definition of RDES3 register
-  */
-#define ETH_DMARXDESC_B2AP        0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
-
-/*---------------------------------------------------------------------------------------------------------------------
-  RDES4 |                   Reserved[31:15]              |             Extended Status [14:0]                          |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES5 |                                            Reserved[31:0]                                                    |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES6 |                                       Receive Time Stamp Low [31:0]                                          |
-  ---------------------------------------------------------------------------------------------------------------------
-  RDES7 |                                       Receive Time Stamp High [31:0]                                         |
-  --------------------------------------------------------------------------------------------------------------------*/
-
-/* Bit definition of RDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV                            0x00002000U  /* PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT                           0x00001000U  /* PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT                           0x00000F00U  /* PTP Message Type */
-#define ETH_DMAPTPRXDESC_PTPMT_SYNC                      0x00000100U  /* SYNC message
-                                                                                   (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP                  0x00000200U  /* FollowUp message
-                                                                                   (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ                  0x00000300U  /* DelayReq message
-                                                                                   (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP                 0x00000400U  /* DelayResp message
-                                                                                   (all clock types) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE        0x00000500U  /* PdelayReq message
-                                                                                   (peer-to-peer transparent clock)
-                                                                                    or Announce message (Ordinary
-                                                                                    or Boundary clock) */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG          0x00000600U  /* PdelayResp message
-                                                                                   (peer-to-peer transparent clock)
-                                                                                    or Management message (Ordinary
-                                                                                    or Boundary clock)  */
-#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U  /* PdelayRespFollowUp message
-                                                                                  (peer-to-peer transparent clock)
-                                                                                   or Signaling message (Ordinary
-                                                                                   or Boundary clock) */
-#define ETH_DMAPTPRXDESC_IPV6PR                          0x00000080U  /* IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4PR                          0x00000040U  /* IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCB                            0x00000020U  /* IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPE                            0x00000010U  /* IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHE                            0x00000008U  /* IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT                            0x00000007U  /* IP Payload Type */
-#define ETH_DMAPTPRXDESC_IPPT_UDP                        0x00000001U  /* UDP payload encapsulated in
-                                                                                   the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_TCP                        0x00000002U  /* TCP payload encapsulated in
-                                                                                   the IP datagram */
-#define ETH_DMAPTPRXDESC_IPPT_ICMP                       0x00000003U  /* ICMP payload encapsulated in
-                                                                                     the IP datagram */
-
-/* Bit definition of RDES6 register */
-#define ETH_DMAPTPRXDESC_RTSL  0xFFFFFFFFU  /* Receive Time Stamp Low */
-
-/* Bit definition of RDES7 register */
-#define ETH_DMAPTPRXDESC_RTSH  0xFFFFFFFFU  /* Receive Time Stamp High */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Frame_settings ETH frame settings
-  * @{
-  */
-#define ETH_MAX_PACKET_SIZE      1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER               14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC                  4U    /*!< Ethernet CRC */
-#define ETH_VLAN_TAG             4U    /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_PAYLOAD          46U    /*!< Minimum Ethernet payload size */
-#define ETH_MAX_PAYLOAD          1500U    /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD  9000U    /*!< Jumbo frame payload size */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Error_Code ETH Error Code
-  * @{
-  */
-#define HAL_ETH_ERROR_NONE             0x00000000U   /*!< No error            */
-#define HAL_ETH_ERROR_PARAM            0x00000001U   /*!< Busy error          */
-#define HAL_ETH_ERROR_BUSY             0x00000002U   /*!< Parameter error     */
-#define HAL_ETH_ERROR_TIMEOUT          0x00000004U   /*!< Timeout error       */
-#define HAL_ETH_ERROR_DMA              0x00000008U   /*!< DMA transfer error  */
-#define HAL_ETH_ERROR_MAC              0x00000010U   /*!< MAC transfer error  */
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U    /*!< Invalid Callback error  */
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
-  * @{
-  */
-#define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
-#define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
-#define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
-#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
-#define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
-#define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
-  * @{
-  */
-#define ETH_CRC_PAD_DISABLE      (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC)
-#define ETH_CRC_PAD_INSERT       0x00000000U
-#define ETH_CRC_INSERT           ETH_DMATXDESC_DP
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
-  * @{
-  */
-#define ETH_CHECKSUM_DISABLE                         ETH_DMATXDESC_CIC_BYPASS
-#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXDESC_CIC_IPV4HEADER
-#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT
-#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXDESC_CIC_TCPUDPICMP_FULL
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
-  * @{
-  */
-#define ETH_VLAN_FILTER_PASS        ETH_DMARXDESC_VLAN
-#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXDESC_AFM
-#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXDESC_SAF
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
-  * @{
-  */
-#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXDESC_DBE
-#define ETH_RECEIVE_ERROR       ETH_DMARXDESC_RE
-#define ETH_RECEIVE_OVERFLOW    ETH_DMARXDESC_OE
-#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXDESC_RWT
-#define ETH_GIANT_PACKET        ETH_DMARXDESC_IPV4HC
-#define ETH_CRC_ERROR           ETH_DMARXDESC_CE
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
-  * @{
-  */
-#define ETH_DMAARBITRATION_RX        ETH_DMABMR_DA
-#define ETH_DMAARBITRATION_RX1_TX1   0x00000000U
-#define ETH_DMAARBITRATION_RX2_TX1   ETH_DMABMR_RTPR_2_1
-#define ETH_DMAARBITRATION_RX3_TX1   ETH_DMABMR_RTPR_3_1
-#define ETH_DMAARBITRATION_RX4_TX1   ETH_DMABMR_RTPR_4_1
-#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
-#define ETH_DMAARBITRATION_TX1_RX1   0x00000000U
-#define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
-#define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
-#define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
-#define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
-#define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
-#define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
-#define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Burst_Mode ETH Burst Mode
-  * @{
-  */
-#define ETH_BURSTLENGTH_FIXED           ETH_DMABMR_FB
-#define ETH_BURSTLENGTH_MIXED           ETH_DMABMR_MB
-#define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
-  * @{
-  */
-#define ETH_TXDMABURSTLENGTH_1BEAT          0x00000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT          0x00000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT          0x00000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT          0x00000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT         0x00001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT         0x00002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    0x01000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    0x01000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   0x01000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   0x01000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   0x01001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  0x01002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
-  * @{
-  */
-#define ETH_RXDMABURSTLENGTH_1BEAT          0x00020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT          0x00040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT          0x00080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT          0x00100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT         0x00200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT         0x00400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    0x01020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    0x01040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   0x01080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   0x01100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   0x01200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  0x01400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
-  * @{
-  */
-#define ETH_DMA_NORMAL_IT                 ETH_DMAIER_NISE
-#define ETH_DMA_ABNORMAL_IT               ETH_DMAIER_AISE
-#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMAIER_FBEIE
-#define ETH_DMA_EARLY_RX_IT               ETH_DMAIER_ERIE
-#define ETH_DMA_EARLY_TX_IT               ETH_DMAIER_ETIE
-#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMAIER_RWTIE
-#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMAIER_RPSIE
-#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMAIER_RBUIE
-#define ETH_DMA_RX_IT                     ETH_DMAIER_RIE
-#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMAIER_TBUIE
-#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMAIER_TPSIE
-#define ETH_DMA_TX_IT                     ETH_DMAIER_TIE
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
-  * @{
-  */
-#define ETH_DMA_NO_ERROR_FLAG                     0x00000000U
-#define ETH_DMA_TX_DATA_TRANS_ERROR_FLAG          ETH_DMASR_EBS_DataTransfTx
-#define ETH_DMA_RX_DATA_TRANS_ERROR_FLAG          0x00000000U
-#define ETH_DMA_READ_TRANS_ERROR_FLAG             ETH_DMASR_EBS_ReadTransf
-#define ETH_DMA_WRITE_TRANS_ERROR_FLAG            0x00000000U
-#define ETH_DMA_DESC_ACCESS_ERROR_FLAG            ETH_DMASR_EBS_DescAccess
-#define ETH_DMA_DATA_BUFF_ACCESS_ERROR_FLAG       0x00000000U
-#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMASR_FBES
-#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMASR_ETS
-#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMASR_RWTS
-#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMASR_RPSS
-#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMASR_RBUS
-#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMASR_TPS
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
-  * @{
-  */
-#define ETH_TRANSMITSTOREFORWARD       ETH_DMAOMR_TSF
-#define ETH_TRANSMITTHRESHOLD_16       ETH_DMAOMR_TTC_16Bytes
-#define ETH_TRANSMITTHRESHOLD_24       ETH_DMAOMR_TTC_24Bytes
-#define ETH_TRANSMITTHRESHOLD_32       ETH_DMAOMR_TTC_32Bytes
-#define ETH_TRANSMITTHRESHOLD_40       ETH_DMAOMR_TTC_40Bytes
-#define ETH_TRANSMITTHRESHOLD_64       ETH_DMAOMR_TTC_64Bytes
-#define ETH_TRANSMITTHRESHOLD_128      ETH_DMAOMR_TTC_128Bytes
-#define ETH_TRANSMITTHRESHOLD_192      ETH_DMAOMR_TTC_192Bytes
-#define ETH_TRANSMITTHRESHOLD_256      ETH_DMAOMR_TTC_256Bytes
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Mode ETH Receive Mode
-  * @{
-  */
-#define ETH_RECEIVESTOREFORWARD        ETH_DMAOMR_RSF
-#define ETH_RECEIVETHRESHOLD8_64       ETH_DMAOMR_RTC_64Bytes
-#define ETH_RECEIVETHRESHOLD8_32       ETH_DMAOMR_RTC_32Bytes
-#define ETH_RECEIVETHRESHOLD8_96       ETH_DMAOMR_RTC_96Bytes
-#define ETH_RECEIVETHRESHOLD8_128      ETH_DMAOMR_RTC_128Bytes
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
-  * @{
-  */
-#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACFCR_PLT_Minus4
-#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACFCR_PLT_Minus28
-#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACFCR_PLT_Minus144
-#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACFCR_PLT_Minus256
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_Speed  ETH Speed
-  * @{
-  */
-#define ETH_SPEED_10M        0x00000000U
-#define ETH_SPEED_100M       0x00004000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
-  * @{
-  */
-#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
-#define ETH_HALFDUPLEX_MODE       0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
-  * @{
-  */
-#define ETH_BACKOFFLIMIT_10  0x00000000U
-#define ETH_BACKOFFLIMIT_8   0x00000020U
-#define ETH_BACKOFFLIMIT_4   0x00000040U
-#define ETH_BACKOFFLIMIT_1   0x00000060U
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
-  * @{
-  */
-#define ETH_SOURCEADDRESS_DISABLE           0x00000000U
-#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
-#define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
-#define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
-#define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
-  * @{
-  */
-#define ETH_VLANTAGCOMPARISON_12BIT    0x00010000U
-#define ETH_VLANTAGCOMPARISON_16BIT    0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_addresses ETH MAC addresses
-  * @{
-  */
-#define ETH_MAC_ADDRESS0     0x00000000U
-#define ETH_MAC_ADDRESS1     0x00000008U
-#define ETH_MAC_ADDRESS2     0x00000010U
-#define ETH_MAC_ADDRESS3     0x00000018U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
-  * @{
-  */
-#define ETH_MAC_PMT_IT           ETH_MACSR_PMTS
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
-  * @{
-  */
-#define ETH_WAKEUP_FRAME_RECIEVED     ETH_MACPMTCSR_WFR
-#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPMTCSR_MPR
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_State_Codes ETH States
-  * @{
-  */
-#define HAL_ETH_STATE_RESET       0x00000000U    /*!< Peripheral not yet Initialized or disabled */
-#define HAL_ETH_STATE_READY       0x00000010U    /*!< Peripheral Communication started           */
-#define HAL_ETH_STATE_BUSY        0x00000020U    /*!< an internal process is ongoing             */
-#define HAL_ETH_STATE_STARTED     0x00000040U    /*!< an internal process is started             */
-#define HAL_ETH_STATE_ERROR       0x000000E0U    /*!< Error State                                */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
-  * @{
-  */
-#define ETH_AUTONEGOTIATION_ENABLE     0x00000001U
-#define ETH_AUTONEGOTIATION_DISABLE    0x00000000U
-
-/**
-  * @}
-  */
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
-  * @{
-  */
-#define ETH_RXPOLLING_MODE      0x00000000U
-#define ETH_RXINTERRUPT_MODE    0x00000001U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
-  * @{
-  */
-#define ETH_CHECKSUM_BY_HARDWARE      0x00000000U
-#define ETH_CHECKSUM_BY_SOFTWARE      0x00000001U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Media_Interface ETH Media Interface
-  * @{
-  */
-#define ETH_MEDIA_INTERFACE_MII       0x00000000U
-#define ETH_MEDIA_INTERFACE_RMII      (SYSCFG_PMC_MII_RMII_SEL)
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Watchdog ETH Watchdog
-  * @{
-  */
-#define ETH_WATCHDOG_ENABLE       0x00000000U
-#define ETH_WATCHDOG_DISABLE      0x00800000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Jabber ETH Jabber
-  * @{
-  */
-#define ETH_JABBER_ENABLE    0x00000000U
-#define ETH_JABBER_DISABLE   0x00400000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
-  * @{
-  */
-#define ETH_INTERFRAMEGAP_96BIT   0x00000000U  /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT   0x00020000U  /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT   0x00040000U  /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT   0x00060000U  /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT   0x00080000U  /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT   0x000A0000U  /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT   0x000C0000U  /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT   0x000E0000U  /*!< minimum IFG between frames during transmission is 40Bit */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
-  * @{
-  */
-#define ETH_CARRIERSENCE_ENABLE   0x00000000U
-#define ETH_CARRIERSENCE_DISABLE  0x00010000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Own ETH Receive Own
-  * @{
-  */
-#define ETH_RECEIVEOWN_ENABLE     0x00000000U
-#define ETH_RECEIVEOWN_DISABLE    0x00002000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
-  * @{
-  */
-#define ETH_LOOPBACKMODE_ENABLE        0x00001000U
-#define ETH_LOOPBACKMODE_DISABLE       0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
-  * @{
-  */
-#define ETH_CHECKSUMOFFLAOD_ENABLE     0x00000400U
-#define ETH_CHECKSUMOFFLAOD_DISABLE    0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
-  * @{
-  */
-#define ETH_RETRYTRANSMISSION_ENABLE   0x00000000U
-#define ETH_RETRYTRANSMISSION_DISABLE  0x00000200U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
-  * @{
-  */
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE     0x00000080U
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE    0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Deferral_Check ETH Deferral Check
-  * @{
-  */
-#define ETH_DEFFERRALCHECK_ENABLE       0x00000010U
-#define ETH_DEFFERRALCHECK_DISABLE      0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_All ETH Receive All
-  * @{
-  */
-#define ETH_RECEIVEALL_ENABLE     0x80000000U
-#define ETH_RECEIVEALL_DISABLE    0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
-  * @{
-  */
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       0x00000200U
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      0x00000300U
-#define ETH_SOURCEADDRFILTER_DISABLE             0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
-  * @{
-  */
-#define ETH_PASSCONTROLFRAMES_BLOCKALL                0x00000040U  /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL              0x00000080U  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U  /*!< MAC forwards control frames that pass the Address Filter. */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
-  * @{
-  */
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE     0x00000000U
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE    0x00000020U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
-  * @{
-  */
-#define ETH_DESTINATIONADDRFILTER_NORMAL    0x00000000U
-#define ETH_DESTINATIONADDRFILTER_INVERSE   0x00000008U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
-  * @{
-  */
-#define ETH_PROMISCUOUS_MODE_ENABLE     0x00000001U
-#define ETH_PROMISCUOUS_MODE_DISABLE    0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
-  * @{
-  */
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    0x00000404U
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE           0x00000004U
-#define ETH_MULTICASTFRAMESFILTER_PERFECT             0x00000000U
-#define ETH_MULTICASTFRAMESFILTER_NONE                0x00000010U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
-  * @{
-  */
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE        0x00000002U
-#define ETH_UNICASTFRAMESFILTER_PERFECT          0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
-  * @{
-  */
-#define ETH_ZEROQUANTAPAUSE_ENABLE     0x00000000U
-#define ETH_ZEROQUANTAPAUSE_DISABLE    0x00000080U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
-  * @{
-  */
-#define ETH_PAUSELOWTHRESHOLD_MINUS4        0x00000000U  /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28       0x00000010U  /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144      0x00000020U  /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256      0x00000030U  /*!< Pause time minus 256 slot times */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
-  * @{
-  */
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  0x00000008U
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
-  * @{
-  */
-#define ETH_RECEIVEFLOWCONTROL_ENABLE       0x00000004U
-#define ETH_RECEIVEFLOWCONTROL_DISABLE      0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
-  * @{
-  */
-#define ETH_TRANSMITFLOWCONTROL_ENABLE      0x00000002U
-#define ETH_TRANSMITFLOWCONTROL_DISABLE     0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
-  * @{
-  */
-#define ETH_MAC_ADDRESSFILTER_SA       0x00000000U
-#define ETH_MAC_ADDRESSFILTER_DA       0x00000008U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
-  * @{
-  */
-#define ETH_MAC_ADDRESSMASK_BYTE6      0x20000000U  /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5      0x10000000U  /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4      0x08000000U  /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3      0x04000000U  /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2      0x02000000U  /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1      0x01000000U  /*!< Mask MAC Address low reg bits [70] */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
-  * @{
-  */
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     0x00000000U  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    0x00004000U  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    0x00008000U  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    0x0000C000U  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     0x00010000U  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     0x00014000U  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     0x00018000U  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     0x0001C000U  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
-  * @{
-  */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      0x00000000U  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      0x00000008U  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      0x00000010U  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     0x00000018U  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
-  * @{
-  */
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   0x00000000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   0x00004000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   0x00008000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   0x0000C000U
-#define ETH_DMAARBITRATION_RXPRIORTX             0x00000002U
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
-  * @{
-  */
-#define ETH_DMATXDESC_LASTSEGMENTS      0x40000000U  /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT      0x20000000U  /*!< First Segment */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
-  * @{
-  */
-#define ETH_DMATXDESC_CHECKSUMBYPASS             0x00000000U   /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER         0x00400000U   /*!< IPv4 header checksum insertion  */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  0x00800000U   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     0x00C00000U   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
-  * @{
-  */
-#define ETH_DMARXDESC_BUFFER1     0x00000000U  /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2     0x00000001U  /*!< DMA Rx Desc Buffer2 */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_PMT_Flags ETH PMT Flags
-  * @{
-  */
-#define ETH_PMT_FLAG_WUFFRPR      0x80000000U  /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR         0x00000040U  /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR          0x00000020U  /*!< Magic Packet Received */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
-  * @{
-  */
-#define ETH_MMC_IT_TGF       0x00200000U  /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC    0x00008000U  /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC     0x00004000U  /*!< When Tx good single col counter reaches half the maximum value */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
-  * @{
-  */
-#define ETH_MMC_IT_RGUF      0x10020000U  /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE      0x10000040U  /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE      0x10000020U  /*!< When Rx crc error counter reaches half the maximum value */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Flags ETH MAC Flags
-  * @{
-  */
-#define ETH_MAC_FLAG_TST     0x00000200U  /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT    0x00000040U  /*!< MMC transmit flag  */
-#define ETH_MAC_FLAG_MMCR    0x00000020U  /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC     0x00000010U  /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT     0x00000008U  /*!< PMT flag (on MAC) */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Flags ETH DMA Flags
-  * @{
-  */
-#define ETH_DMA_FLAG_TST               0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT               0x10000000U  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC               0x08000000U  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR    0x01000000U  /*!< Error bits 0-write transfer, 1-read transfer */
-#define ETH_DMA_FLAG_ACCESSERROR       0x02000000U  /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS               0x00010000U  /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS               0x00008000U  /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER                0x00004000U  /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE               0x00002000U  /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET                0x00000400U  /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT               0x00000200U  /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS               0x00000100U  /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU               0x00000080U  /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R                 0x00000040U  /*!< Receive flag */
-#define ETH_DMA_FLAG_TU                0x00000020U  /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO                0x00000010U  /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT               0x00000008U  /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU               0x00000004U  /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS               0x00000002U  /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T                 0x00000001U  /*!< Transmit flag */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
-  * @{
-  */
-#define ETH_MAC_IT_TST       0x00000200U  /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT      0x00000040U  /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR      0x00000020U  /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC       0x00000010U  /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT       0x00000008U  /*!< PMT interrupt (on MAC) */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
-  * @{
-  */
-#define ETH_DMA_IT_TST       0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT       0x10000000U  /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC       0x08000000U  /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS       0x00010000U  /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS       0x00008000U  /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER        0x00004000U  /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE       0x00002000U  /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET        0x00000400U  /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT       0x00000200U  /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS       0x00000100U  /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU       0x00000080U  /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R         0x00000040U  /*!< Receive interrupt */
-#define ETH_DMA_IT_TU        0x00000020U  /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO        0x00000010U  /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT       0x00000008U  /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU       0x00000004U  /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS       0x00000002U  /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T         0x00000001U  /*!< Transmit interrupt */
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
-  * @{
-  */
-#define ETH_DMA_TRANSMITPROCESS_STOPPED     0x00000000U  /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING    0x00100000U  /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING     0x00200000U  /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING     0x00300000U  /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED   0x00600000U  /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING     0x00700000U  /*!< Running - closing Rx descriptor */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
-  * @{
-  */
-#define ETH_DMA_RECEIVEPROCESS_STOPPED      0x00000000U  /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING     0x00020000U  /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING      0x00060000U  /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED    0x00080000U  /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING      0x000A0000U  /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING      0x000E0000U  /*!< Running - queuing the receive frame into host memory */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DMA_overflow ETH DMA overflow
-  * @{
-  */
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      0x10000000U  /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U  /*!< Overflow bit for missed frame counter */
-/**
-  * @}
-  */
-/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
-  * @{
-  */
-#define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
-#define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Macros ETH Exported Macros
-  * @{
-  */
-
-/** @brief Reset ETH handle state
-  * @param  __HANDLE__: specifies the ETH handle.
-  * @retval None
-  */
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
-                                                      (__HANDLE__)->MspInitCallback = NULL;             \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                    } while(0)
-#else
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
-                                                    } while(0)
-#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
-  *   enabled @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER \
-                                                                            |= (__INTERRUPT__))
-
-/**
-  * @brief  Disables the specified ETHERNET DMA interrupts.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
-  *   disabled. @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER \
-                                                                            &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
-  * @retval The ETH DMA IT Source enabled or disabled
-  */
-#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMAIER &\
-                                                                      (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Gets the ETHERNET DMA IT pending bit.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
-  * @retval The state of ETH DMA IT (SET or RESET)
-  */
-#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMASR &\
-                                                               (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the ETHERNET DMA IT pending bit.
-  * @param  __HANDLE__   : ETH Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
-  * @retval None
-  */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
-  * @retval The state of ETH DMA FLAG (SET or RESET).
-  */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &\
-                                                                         ( __FLAG__)) == ( __FLAG__))
-
-/**
-  * @brief  Clears the specified ETHERNET DMA flag.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
-  * @retval The state of ETH DMA FLAG (SET or RESET).
-  */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMASR = ( __FLAG__))
-
-
-/**
-  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
-  * @param  __HANDLE__: ETH Handle
-  * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
-  * @retval The state of ETH MAC IT (SET or RESET).
-  */
-#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACSR &\
-                                                                              ( __INTERRUPT__)) == ( __INTERRUPT__))
-
-/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */
-#define ETH_WAKEUP_EXTI_LINE  0x00080000U
-
-/**
-  * @brief Enable the ETH WAKEUP Exti Line.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
-  *   @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR |= (__EXTI_LINE__))
-
-/**
-  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE
-  * @retval EXTI ETH WAKEUP Line Status.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief Clear the ETH WAKEUP Exti flag.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None.
-  */
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  enable rising edge interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
-  *  @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \
-  (EXTI->RTSR |= (__EXTI_LINE__))
-
-/**
-  * @brief  enable falling edge interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
-  *  @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\
-  (EXTI->FTSR |= (__EXTI_LINE__))
-
-/**
-  * @brief  enable falling edge interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
-  *  @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\
-  (EXTI->FTSR |= (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
-  *  @arg ETH_WAKEUP_EXTI_LINE
-  * @retval None
-  */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \
-                                                           (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__))
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup ETH_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ETH_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de initialization functions  **********************************/
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
-                                           pETH_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup ETH_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
-
-HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
-HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
-                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
-HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
-
-#ifdef HAL_ETH_USE_PTP
-HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
-HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
-HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
-HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
-HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
-                                            ETH_TimeTypeDef *timeoffset);
-HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
-HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
-HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
-HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
-#endif /* HAL_ETH_USE_PTP */
-
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
-
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                           uint32_t RegValue);
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                          uint32_t *pRegValue);
-
-void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
-void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
-void              HAL_ETH_TxFreeCallback(uint32_t *buff);
-void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
-/**
-  * @}
-  */
-
-/** @addtogroup ETH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-/* MAC & DMA Configuration APIs  **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
-HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
-void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
-
-/* MAC VLAN Processing APIs    ************************************************/
-void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
-                                              uint32_t VLANIdentifier);
-
-/* MAC L2 Packet Filtering APIs  **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
-                                                const uint8_t *pMACAddr);
-
-/* MAC Power Down APIs    *****************************************************/
-void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
-                                             const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
-void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
-
-/**
-  * @}
-  */
-
-/** @addtogroup ETH_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ETH */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F7xx_HAL_ETH_H */
diff --git a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c
deleted file mode 100644
index 73f72d1..0000000
--- a/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c
+++ /dev/null
@@ -1,3308 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_eth.c
-  * @author  MCD Application Team
-  * @brief   ETH HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Ethernet (ETH) peripheral:
-  *           + Initialization and deinitialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-     [..]
-     The ETH HAL driver can be used as follows:
-
-      (#)Declare a ETH_HandleTypeDef handle structure, for example:
-         ETH_HandleTypeDef  heth;
-
-      (#)Fill parameters of Init structure in heth handle
-
-      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
-
-      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
-          (##) Enable the Ethernet interface clock using
-                (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
-                (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
-                (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()
-
-          (##) Initialize the related GPIO clocks
-          (##) Configure Ethernet pinout
-          (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
-
-      (#) Ethernet data reception is asynchronous, so call the following API
-          to start the listening mode:
-          (##) HAL_ETH_Start():
-               This API starts the MAC and DMA transmission and reception process,
-               without enabling end of transfer interrupts, in this mode user
-               has to poll for data reception by calling HAL_ETH_ReadData()
-          (##) HAL_ETH_Start_IT():
-               This API starts the MAC and DMA transmission and reception process,
-               end of transfer interrupts are enabled in this mode,
-               HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
-
-      (#) When data is received user can call the following API to get received data:
-          (##) HAL_ETH_ReadData(): Read a received packet
-
-      (#) For transmission path, two APIs are available:
-         (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
-         (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
-              HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
-
-      (#) Communication with an external PHY device:
-         (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
-         (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
-
-      (#) Configure the Ethernet MAC after ETH peripheral initialization
-          (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
-          (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
-
-      (#) Configure the Ethernet DMA after ETH peripheral initialization
-          (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
-          (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
-
-      (#) Configure the Ethernet PTP after ETH peripheral initialization
-          (##) Define HAL_ETH_USE_PTP to use PTP APIs.
-          (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef
-          (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef
-          (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
-          (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
-          (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
-          (##) HAL_ETH_PTP_AddendUpdate(): Update the Addend register
-          (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
-          (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
-          (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
-
-      -@- The ARP offload feature is not supported in this driver.
-
-      -@- The PTP offload feature is not supported in this driver.
-
-  *** Callback registration ***
-  =============================================
-
-  The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-  Use Function HAL_ETH_RegisterCallback() to register an interrupt callback.
-
-  Function HAL_ETH_RegisterCallback() allows to register following callbacks:
-    (+) TxCpltCallback   : Tx Complete Callback.
-    (+) RxCpltCallback   : Rx Complete Callback.
-    (+) ErrorCallback    : Error Callback.
-    (+) PMTCallback      : Power Management Callback
-    (+) EEECallback      : EEE Callback.
-    (+) WakeUpCallback   : Wake UP Callback
-    (+) MspInitCallback  : MspInit Callback.
-    (+) MspDeInitCallback: MspDeInit Callback.
-
-  This function takes as parameters the HAL peripheral handle, the Callback ID
-  and a pointer to the user callback function.
-
-  For specific callbacks RxAllocateCallback use dedicated register callbacks:
-  respectively HAL_ETH_RegisterRxAllocateCallback().
-
-  For specific callbacks RxLinkCallback use dedicated register callbacks:
-  respectively HAL_ETH_RegisterRxLinkCallback().
-
-  For specific callbacks TxFreeCallback use dedicated register callbacks:
-  respectively HAL_ETH_RegisterTxFreeCallback().
-
-  For specific callbacks TxPtpCallback use dedicated register callbacks:
-  respectively HAL_ETH_RegisterTxPtpCallback().
-
-  Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-  This function allows to reset following callbacks:
-    (+) TxCpltCallback   : Tx Complete Callback.
-    (+) RxCpltCallback   : Rx Complete Callback.
-    (+) ErrorCallback    : Error Callback.
-    (+) PMTCallback      : Power Management Callback
-    (+) EEECallback      : EEE Callback.
-    (+) WakeUpCallback   : Wake UP Callback
-    (+) MspInitCallback  : MspInit Callback.
-    (+) MspDeInitCallback: MspDeInit Callback.
-
-  For specific callbacks RxAllocateCallback use dedicated unregister callbacks:
-  respectively HAL_ETH_UnRegisterRxAllocateCallback().
-
-  For specific callbacks RxLinkCallback use dedicated unregister callbacks:
-  respectively HAL_ETH_UnRegisterRxLinkCallback().
-
-  For specific callbacks TxFreeCallback use dedicated unregister callbacks:
-  respectively HAL_ETH_UnRegisterTxFreeCallback().
-
-  For specific callbacks TxPtpCallback use dedicated unregister callbacks:
-  respectively HAL_ETH_UnRegisterTxPtpCallback().
-
-  By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
-  all callbacks are set to the corresponding weak functions:
-  examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback().
-  Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when
-  these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit
-  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-  Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
-  Exception done MspInit/MspDeInit that can be registered/unregistered
-  in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
-  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-  using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit
-  or HAL_ETH_Init function.
-
-  When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
-  not defined, the callback registration feature is not available and all callbacks
-  are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal.h"
-
-/** @addtogroup STM32F7xx_HAL_Driver
-  * @{
-  */
-#ifdef HAL_ETH_MODULE_ENABLED
-
-#if defined(ETH)
-
-/** @defgroup ETH ETH
-  * @brief ETH HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup ETH_Private_Constants ETH Private Constants
-  * @{
-  */
-#define ETH_MACCR_MASK          0xFFFB7F7CU
-#define ETH_MACECR_MASK         0x3F077FFFU
-#define ETH_MACFFR_MASK         0x800007FFU
-#define ETH_MACWTR_MASK         0x0000010FU
-#define ETH_MACTFCR_MASK        0xFFFF00F2U
-#define ETH_MACRFCR_MASK        0x00000003U
-#define ETH_MTLTQOMR_MASK       0x00000072U
-#define ETH_MTLRQOMR_MASK       0x0000007BU
-
-#define ETH_DMAMR_MASK          0x00007802U
-#define ETH_DMASBMR_MASK        0x0000D001U
-#define ETH_DMACCR_MASK         0x00013FFFU
-#define ETH_DMACTCR_MASK        0x003F1010U
-#define ETH_DMACRCR_MASK        0x803F0000U
-#define ETH_MACPMTCSR_MASK      (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \
-                                 ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU)
-
-/* Timeout values */
-#define ETH_SWRESET_TIMEOUT     500U
-#define ETH_MDIO_BUS_TIMEOUT    1000U
-
-#define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \
-                                              ETH_DMARXDESC_OE  | ETH_DMARXDESC_RWT |\
-                                              ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\
-                                              ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE))
-
-#define ETH_MAC_US_TICK         1000000U
-
-#define ETH_MACTSCR_MASK        0x0087FF2FU
-
-#define ETH_PTPTSHR_VALUE       0xFFFFFFFFU
-#define ETH_PTPTSLR_VALUE       0xBB9ACA00U
-
-/* Ethernet MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK    0xFFFFFFE3U
-
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY     0x00000001U
-
-/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK    0xFD20810FU
-
-/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK   0x0000FF41U
-
-/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK   0xF8DE3F23U
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE      (uint32_t)(ETH_MAC_BASE + 0x40U)  /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE      (uint32_t)(ETH_MAC_BASE + 0x44U)  /* ETHERNET MAC address low offset */
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define  ETH_DMARXDESC_FRAMELENGTHSHIFT            16U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ETH_Private_Macros ETH Private Macros
-  * @{
-  */
-/* Helper macros for TX descriptor handling */
-#define INCR_TX_DESC_INDEX(inx, offset) do {\
-                                             (inx) += (offset);\
-                                             if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
-                                             (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
-                                           } while (0)
-
-/* Helper macros for RX descriptor handling */
-#define INCR_RX_DESC_INDEX(inx, offset) do {\
-                                             (inx) += (offset);\
-                                             if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
-                                             (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
-                                           } while (0)
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ETH_Private_Functions   ETH Private Functions
-  * @{
-  */
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
-static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
-static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
-                                           uint32_t ItMode);
-static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
-static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
-static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-#ifdef HAL_ETH_USE_PTP
-static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset);
-#endif /* HAL_ETH_USE_PTP */
-
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup ETH_Exported_Functions ETH Exported Functions
-  * @{
-  */
-
-/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          deinitialize the ETH peripheral:
-
-      (+) User must Implement HAL_ETH_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO and NVIC ).
-
-      (+) Call the function HAL_ETH_Init() to configure the selected device with
-          the selected configuration:
-        (++) MAC address
-        (++) Media interface (MII or RMII)
-        (++) Rx DMA Descriptors Tab
-        (++) Tx DMA Descriptors Tab
-        (++) Length of Rx Buffers
-
-      (+) Call the function HAL_ETH_DeInit() to restore the default configuration
-          of the selected ETH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the Ethernet peripheral registers.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
-{
-  uint32_t tickstart;
-
-  if (heth == NULL)
-  {
-    return HAL_ERROR;
-  }
-  if (heth->gState == HAL_ETH_STATE_RESET)
-  {
-    heth->gState = HAL_ETH_STATE_BUSY;
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-
-    ETH_InitCallbacksToDefault(heth);
-
-    if (heth->MspInitCallback == NULL)
-    {
-      heth->MspInitCallback = HAL_ETH_MspInit;
-    }
-
-    /* Init the low level hardware */
-    heth->MspInitCallback(heth);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
-    HAL_ETH_MspInit(heth);
-
-#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
-  }
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  /* Select MII or RMII Mode*/
-  SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
-  SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
-  /* Dummy read to sync SYSCFG with ETH */
-  (void)SYSCFG->PMC;
-
-  /* Ethernet Software reset */
-  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
-  /* After reset all the registers holds their respective reset values */
-  SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait for software reset */
-  while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U)
-  {
-    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
-    {
-      /* Set Error Code */
-      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
-      /* Set State as Error */
-      heth->gState = HAL_ETH_STATE_ERROR;
-      /* Return Error */
-      return HAL_ERROR;
-    }
-  }
-
-
-  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
-  ETH_MACDMAConfig(heth);
-
-
-  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
-  ETH_DMATxDescListInit(heth);
-
-  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
-  ETH_DMARxDescListInit(heth);
-
-  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
-  ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
-
-  /* Disable MMC Interrupts */
-  SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM);
-
-  /* Disable Rx MMC Interrupts */
-  SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \
-          ETH_MMCRIMR_RFCEM);
-
-  /* Disable Tx MMC Interrupts */
-  SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \
-          ETH_MMCTIMR_TGFSCM);
-
-  heth->ErrorCode = HAL_ETH_ERROR_NONE;
-  heth->gState = HAL_ETH_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the ETH peripheral.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
-{
-  /* Set the ETH peripheral state to BUSY */
-  heth->gState = HAL_ETH_STATE_BUSY;
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-
-  if (heth->MspDeInitCallback == NULL)
-  {
-    heth->MspDeInitCallback = HAL_ETH_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  heth->MspDeInitCallback(heth);
-#else
-
-  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
-  HAL_ETH_MspDeInit(heth);
-
-#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
-
-  /* Set ETH HAL state to Disabled */
-  heth->gState = HAL_ETH_STATE_RESET;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the ETH MSP.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_MspInit could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  DeInitializes ETH MSP.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_MspDeInit could be implemented in the user file
-  */
-}
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User ETH Callback
-  *         To be used instead of the weak predefined callback
-  * @param heth eth handle
-  * @param CallbackID ID of the callback to be registered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
-  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
-  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
-  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
-  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
-  * @param pCallback pointer to the Callback function
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
-                                           pETH_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-    return HAL_ERROR;
-  }
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ETH_TX_COMPLETE_CB_ID :
-        heth->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_ETH_RX_COMPLETE_CB_ID :
-        heth->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_ETH_ERROR_CB_ID :
-        heth->ErrorCallback = pCallback;
-        break;
-
-      case HAL_ETH_PMT_CB_ID :
-        heth->PMTCallback = pCallback;
-        break;
-
-
-      case HAL_ETH_WAKEUP_CB_ID :
-        heth->WakeUpCallback = pCallback;
-        break;
-
-      case HAL_ETH_MSPINIT_CB_ID :
-        heth->MspInitCallback = pCallback;
-        break;
-
-      case HAL_ETH_MSPDEINIT_CB_ID :
-        heth->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (heth->gState == HAL_ETH_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ETH_MSPINIT_CB_ID :
-        heth->MspInitCallback = pCallback;
-        break;
-
-      case HAL_ETH_MSPDEINIT_CB_ID :
-        heth->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an ETH Callback
-  *         ETH callback is redirected to the weak predefined callback
-  * @param heth eth handle
-  * @param CallbackID ID of the callback to be unregistered
-  *        This parameter can be one of the following values:
-  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
-  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
-  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
-  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
-  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ETH_TX_COMPLETE_CB_ID :
-        heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
-        break;
-
-      case HAL_ETH_RX_COMPLETE_CB_ID :
-        heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
-        break;
-
-      case HAL_ETH_ERROR_CB_ID :
-        heth->ErrorCallback = HAL_ETH_ErrorCallback;
-        break;
-
-      case HAL_ETH_PMT_CB_ID :
-        heth->PMTCallback = HAL_ETH_PMTCallback;
-        break;
-
-
-      case HAL_ETH_WAKEUP_CB_ID :
-        heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
-        break;
-
-      case HAL_ETH_MSPINIT_CB_ID :
-        heth->MspInitCallback = HAL_ETH_MspInit;
-        break;
-
-      case HAL_ETH_MSPDEINIT_CB_ID :
-        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (heth->gState == HAL_ETH_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_ETH_MSPINIT_CB_ID :
-        heth->MspInitCallback = HAL_ETH_MspInit;
-        break;
-
-      case HAL_ETH_MSPDEINIT_CB_ID :
-        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
-  *  @brief ETH Transmit and Receive functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the ETH
-    data transfer.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables Ethernet MAC and DMA reception and transmission
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
-{
-  uint32_t tmpreg1;
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    heth->gState = HAL_ETH_STATE_BUSY;
-
-    /* Set number of descriptors to build */
-    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
-
-    /* Build all descriptors */
-    ETH_UpdateDescriptor(heth);
-
-    /* Enable the MAC transmission */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Flush Transmit FIFO */
-    ETH_FlushTransmitFIFO(heth);
-
-    /* Enable the DMA transmission */
-    SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
-
-    /* Enable the DMA reception */
-    SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
-
-    heth->gState = HAL_ETH_STATE_STARTED;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
-{
-  uint32_t tmpreg1;
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    heth->gState = HAL_ETH_STATE_BUSY;
-
-    /* save IT mode to ETH Handle */
-    heth->RxDescList.ItMode = 1U;
-
-    /* Set number of descriptors to build */
-    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
-
-    /* Build all descriptors */
-    ETH_UpdateDescriptor(heth);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Enable the DMA transmission */
-    SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
-
-    /* Enable the DMA reception */
-    SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
-
-    /* Flush Transmit FIFO */
-    ETH_FlushTransmitFIFO(heth);
-
-
-    /* Enable the MAC transmission */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
-    /* Enable ETH DMA interrupts:
-    - Tx complete interrupt
-    - Rx complete interrupt
-    - Fatal bus interrupt
-    */
-    __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE  |
-                                   ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE));
-
-    heth->gState = HAL_ETH_STATE_STARTED;
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Stop Ethernet MAC and DMA reception/transmission
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
-{
-  uint32_t tmpreg1;
-
-  if (heth->gState == HAL_ETH_STATE_STARTED)
-  {
-    /* Set the ETH peripheral state to BUSY */
-    heth->gState = HAL_ETH_STATE_BUSY;
-
-    /* Disable the DMA transmission */
-    CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
-
-    /* Disable the DMA reception */
-    CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
-
-    /* Disable the MAC reception */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Flush Transmit FIFO */
-    ETH_FlushTransmitFIFO(heth);
-
-    /* Disable the MAC transmission */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    heth->gState = HAL_ETH_STATE_READY;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
-{
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint32_t descindex;
-  uint32_t tmpreg1;
-
-  if (heth->gState == HAL_ETH_STATE_STARTED)
-  {
-    /* Set the ETH peripheral state to BUSY */
-    heth->gState = HAL_ETH_STATE_BUSY;
-
-    __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE  |
-                                    ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE));
-
-    /* Disable the DMA transmission */
-    CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST);
-
-    /* Disable the DMA reception */
-    CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR);
-
-    /* Disable the MAC reception */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Flush Transmit FIFO */
-    ETH_FlushTransmitFIFO(heth);
-
-    /* Disable the MAC transmission */
-    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACCR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACCR = tmpreg1;
-
-    /* Clear IOC bit to all Rx descriptors */
-    for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
-    {
-      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
-      SET_BIT(dmarxdesc->DESC1, ETH_DMARXDESC_DIC);
-    }
-
-    heth->RxDescList.ItMode = 0U;
-
-    heth->gState = HAL_ETH_STATE_READY;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sends an Ethernet Packet in polling mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pTxConfig: Hold the configuration of packet to be transmitted
-  * @param  Timeout: timeout value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
-{
-  uint32_t tickstart;
-  ETH_DMADescTypeDef *dmatxdesc;
-
-  if (pTxConfig == NULL)
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if (heth->gState == HAL_ETH_STATE_STARTED)
-  {
-    /* Config DMA Tx descriptor by Tx Packet info */
-    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
-    {
-      /* Set the ETH error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
-      return HAL_ERROR;
-    }
-
-    /* Ensure completion of descriptor preparation before transmission start */
-    __DSB();
-
-    dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
-
-    /* Incr current tx desc index */
-    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
-
-    /* Start transmission */
-    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
-    WRITE_REG(heth->Instance->DMATPDR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
-
-    tickstart = HAL_GetTick();
-
-    /* Wait for data to be transmitted or timeout occurred */
-    while ((dmatxdesc->DESC0 & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
-    {
-      if ((heth->Instance->DMASR & ETH_DMASR_FBES) != (uint32_t)RESET)
-      {
-        heth->ErrorCode |= HAL_ETH_ERROR_DMA;
-        heth->DMAErrorCode = heth->Instance->DMASR;
-        /* Return function status */
-        return HAL_ERROR;
-      }
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
-          /* Clear TX descriptor so that we can proceed */
-          dmatxdesc->DESC0 = (ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
-          return HAL_ERROR;
-        }
-      }
-    }
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Sends an Ethernet Packet in interrupt mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pTxConfig: Hold the configuration of packet to be transmitted
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
-{
-  if (pTxConfig == NULL)
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if (heth->gState == HAL_ETH_STATE_STARTED)
-  {
-    /* Save the packet pointer to release.  */
-    heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
-
-    /* Config DMA Tx descriptor by Tx Packet info */
-    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
-    {
-      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
-      return HAL_ERROR;
-    }
-
-    /* Ensure completion of descriptor preparation before transmission start */
-    __DSB();
-
-    /* Incr current tx desc index */
-    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
-
-    /* Start transmission */
-    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
-    if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
-    {
-      /* Clear TBUS ETHERNET DMA flag */
-      (heth->Instance)->DMASR = ETH_DMASR_TBUS;
-      /* Resume DMA transmission*/
-      (heth->Instance)->DMATPDR = 0U;
-    }
-
-    return HAL_OK;
-
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Read a received packet.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pAppBuff: Pointer to an application buffer to receive the packet.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
-{
-  uint32_t descidx;
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint32_t desccnt = 0U;
-  uint32_t desccntmax;
-  uint32_t bufflength;
-  uint8_t rxdataready = 0U;
-
-  if (pAppBuff == NULL)
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if (heth->gState != HAL_ETH_STATE_STARTED)
-  {
-    return HAL_ERROR;
-  }
-
-  descidx = heth->RxDescList.RxDescIdx;
-  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
-  desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
-
-  /* Check if descriptor is not owned by DMA */
-  while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
-         && (rxdataready == 0U))
-  {
-    if (READ_BIT(dmarxdesc->DESC0,  ETH_DMARXDESC_LS)  != (uint32_t)RESET)
-    {
-      /* Get timestamp high */
-      heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC7;
-      /* Get timestamp low */
-      heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc->DESC6;
-    }
-    if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
-    {
-      /* Check first descriptor */
-      if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET)
-      {
-        heth->RxDescList.RxDescCnt = 0;
-        heth->RxDescList.RxDataLength = 0;
-      }
-
-      /* Get the Frame Length of the received packet */
-      bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT);
-
-      /* Check if last descriptor */
-      if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET)
-      {
-        /* Save Last descriptor index */
-        heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0;
-
-        /* Packet ready */
-        rxdataready = 1;
-      }
-
-      /* Link data */
-      WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2);
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Link callback*/
-      heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
-                           (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
-#else
-      /* Link callback */
-      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
-                             (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-      heth->RxDescList.RxDescCnt++;
-      heth->RxDescList.RxDataLength += bufflength;
-
-      /* Clear buffer pointer */
-      dmarxdesc->BackupAddr0 = 0;
-    }
-
-    /* Increment current rx descriptor index */
-    INCR_RX_DESC_INDEX(descidx, 1U);
-    /* Get current descriptor address */
-    dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
-    desccnt++;
-  }
-
-  heth->RxDescList.RxBuildDescCnt += desccnt;
-  if ((heth->RxDescList.RxBuildDescCnt) != 0U)
-  {
-    /* Update Descriptors */
-    ETH_UpdateDescriptor(heth);
-  }
-
-  heth->RxDescList.RxDescIdx = descidx;
-
-  if (rxdataready == 1U)
-  {
-    /* Return received packet */
-    *pAppBuff = heth->RxDescList.pRxStart;
-    /* Reset first element */
-    heth->RxDescList.pRxStart = NULL;
-
-    return HAL_OK;
-  }
-
-  /* Packet not ready */
-  return HAL_ERROR;
-}
-
-/**
-  * @brief  This function gives back Rx Desc of the last received Packet
-  *         to the DMA, so ETH DMA will be able to use these descriptors
-  *         to receive next Packets.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
-{
-  uint32_t descidx;
-  uint32_t tailidx;
-  uint32_t desccount;
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint8_t *buff = NULL;
-  uint8_t allocStatus = 1U;
-
-  descidx = heth->RxDescList.RxBuildDescIdx;
-  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
-  desccount = heth->RxDescList.RxBuildDescCnt;
-
-  while ((desccount > 0U) && (allocStatus != 0U))
-  {
-    /* Check if a buffer's attached the descriptor */
-    if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
-    {
-      /* Get a new buffer. */
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Allocate callback*/
-      heth->rxAllocateCallback(&buff);
-#else
-      /* Allocate callback */
-      HAL_ETH_RxAllocateCallback(&buff);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-      if (buff == NULL)
-      {
-        allocStatus = 0U;
-      }
-      else
-      {
-        WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
-        WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff);
-      }
-    }
-
-    if (allocStatus != 0U)
-    {
-      if (heth->RxDescList.ItMode == 0U)
-      {
-        WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_DIC | ETH_DMARXDESC_RCH);
-      }
-      else
-      {
-        WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_RCH);
-      }
-
-      SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN);
-
-      /* Increment current rx descriptor index */
-      INCR_RX_DESC_INDEX(descidx, 1U);
-      /* Get current descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
-      desccount--;
-    }
-  }
-
-  if (heth->RxDescList.RxBuildDescCnt != desccount)
-  {
-    /* Set the tail pointer index */
-    tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
-
-    /* DMB instruction to avoid race condition */
-    __DMB();
-
-    /* Set the Tail pointer address */
-    WRITE_REG(heth->Instance->DMARPDR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
-
-    heth->RxDescList.RxBuildDescIdx = descidx;
-    heth->RxDescList.RxBuildDescCnt = desccount;
-  }
-}
-
-/**
-  * @brief  Register the Rx alloc callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  rxAllocateCallback: pointer to function to alloc buffer
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
-                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
-{
-  if (rxAllocateCallback == NULL)
-  {
-    /* No buffer to save */
-    return HAL_ERROR;
-  }
-
-  /* Set function to allocate buffer */
-  heth->rxAllocateCallback = rxAllocateCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unregister the Rx alloc callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
-{
-  /* Set function to allocate buffer */
-  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Rx Allocate callback.
-  * @param  buff: pointer to allocated buffer
-  * @retval None
-  */
-__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(buff);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_RxAllocateCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Rx Link callback.
-  * @param  pStart: pointer to packet start
-  * @param  pEnd: pointer to packet end
-  * @param  buff: pointer to received data
-  * @param  Length: received data length
-  * @retval None
-  */
-__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(pStart);
-  UNUSED(pEnd);
-  UNUSED(buff);
-  UNUSED(Length);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_RxLinkCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Set the Rx link data function.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  rxLinkCallback: pointer to function to link data
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
-{
-  if (rxLinkCallback == NULL)
-  {
-    /* No buffer to save */
-    return HAL_ERROR;
-  }
-
-  /* Set function to link data */
-  heth->rxLinkCallback = rxLinkCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unregister the Rx link callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
-{
-  /* Set function to allocate buffer */
-  heth->rxLinkCallback = HAL_ETH_RxLinkCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the error state of the last received packet.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pErrorCode: pointer to uint32_t to hold the error code
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
-{
-  /* Get error bits. */
-  *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXDESC_ERRORS_MASK);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the Tx free function.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  txFreeCallback: pointer to function to release the packet
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
-{
-  if (txFreeCallback == NULL)
-  {
-    /* No buffer to save */
-    return HAL_ERROR;
-  }
-
-  /* Set function to free transmmitted packet */
-  heth->txFreeCallback = txFreeCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unregister the Tx free callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
-{
-  /* Set function to allocate buffer */
-  heth->txFreeCallback = HAL_ETH_TxFreeCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Tx Free callback.
-  * @param  buff: pointer to buffer to free
-  * @retval None
-  */
-__weak void HAL_ETH_TxFreeCallback(uint32_t *buff)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(buff);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_TxFreeCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Release transmitted Tx packets.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
-{
-  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
-  uint32_t numOfBuf =  dmatxdesclist->BuffersInUse;
-  uint32_t idx =       dmatxdesclist->releaseIndex;
-  uint8_t pktTxStatus = 1U;
-  uint8_t pktInUse;
-#ifdef HAL_ETH_USE_PTP
-  ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
-#endif /* HAL_ETH_USE_PTP */
-
-  /* Loop through buffers in use.  */
-  while ((numOfBuf != 0U) && (pktTxStatus != 0U))
-  {
-    pktInUse = 1U;
-    numOfBuf--;
-    /* If no packet, just examine the next packet.  */
-    if (dmatxdesclist->PacketAddress[idx] == NULL)
-    {
-      /* No packet in use, skip to next.  */
-      INCR_TX_DESC_INDEX(idx, 1U);
-      pktInUse = 0U;
-    }
-
-    if (pktInUse != 0U)
-    {
-      /* Determine if the packet has been transmitted.  */
-      if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U)
-      {
-#ifdef HAL_ETH_USE_PTP
-        if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_LS)
-            && (heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_TTSS))
-        {
-          /* Get timestamp low */
-          timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6;
-          /* Get timestamp high */
-          timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7;
-        }
-        else
-        {
-          timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
-        }
-#endif /* HAL_ETH_USE_PTP */
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-        /*Call registered callbacks*/
-#ifdef HAL_ETH_USE_PTP
-        /* Handle Ptp  */
-        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
-        {
-          heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
-        }
-#endif  /* HAL_ETH_USE_PTP */
-        /* Release the packet.  */
-        heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
-#else
-        /* Call callbacks */
-#ifdef HAL_ETH_USE_PTP
-        /* Handle Ptp  */
-        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
-        {
-          HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
-        }
-#endif  /* HAL_ETH_USE_PTP */
-        /* Release the packet.  */
-        HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-        /* Clear the entry in the in-use array.  */
-        dmatxdesclist->PacketAddress[idx] = NULL;
-
-        /* Update the transmit relesae index and number of buffers in use.  */
-        INCR_TX_DESC_INDEX(idx, 1U);
-        dmatxdesclist->BuffersInUse = numOfBuf;
-        dmatxdesclist->releaseIndex = idx;
-      }
-      else
-      {
-        /* Get out of the loop!  */
-        pktTxStatus = 0U;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-#ifdef HAL_ETH_USE_PTP
-/**
-  * @brief  Set the Ethernet PTP configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
-  *         the configuration information for PTP
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
-{
-  uint32_t tmpTSCR;
-  ETH_TimeTypeDef time;
-
-  if (ptpconfig == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Mask the Timestamp Trigger interrupt */
-  CLEAR_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM);
-
-  tmpTSCR = ptpconfig->Timestamp |
-            ((uint32_t)ptpconfig->TimestampUpdate << ETH_PTPTSCR_TSFCU_Pos) |
-            ((uint32_t)ptpconfig->TimestampAll << ETH_PTPTSCR_TSSARFE_Pos) |
-            ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_PTPTSCR_TSSSR_Pos) |
-            ((uint32_t)ptpconfig->TimestampV2 << ETH_PTPTSCR_TSPTPPSV2E_Pos) |
-            ((uint32_t)ptpconfig->TimestampEthernet << ETH_PTPTSCR_TSSPTPOEFE_Pos) |
-            ((uint32_t)ptpconfig->TimestampIPv6 << ETH_PTPTSCR_TSSIPV6FE_Pos) |
-            ((uint32_t)ptpconfig->TimestampIPv4 << ETH_PTPTSCR_TSSIPV4FE_Pos) |
-            ((uint32_t)ptpconfig->TimestampEvent << ETH_PTPTSCR_TSSEME_Pos) |
-            ((uint32_t)ptpconfig->TimestampMaster << ETH_PTPTSCR_TSSMRME_Pos) |
-            ((uint32_t)ptpconfig->TimestampFilter << ETH_PTPTSCR_TSPFFMAE_Pos) |
-            ((uint32_t)ptpconfig->TimestampClockType << ETH_PTPTSCR_TSCNT_Pos);
-
-  /* Write to MACTSCR */
-  MODIFY_REG(heth->Instance->PTPTSCR, ETH_MACTSCR_MASK, tmpTSCR);
-
-  /* Enable Timestamp */
-  SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE);
-  WRITE_REG(heth->Instance->PTPSSIR, ptpconfig->TimestampSubsecondInc);
-  WRITE_REG(heth->Instance->PTPTSAR, ptpconfig->TimestampAddend);
-
-  /* Enable Timestamp */
-  if (ptpconfig->TimestampAddendUpdate == ENABLE)
-  {
-    SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU);
-    while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0)
-    {
-
-    }
-  }
-
-  /* Enable Update mode */
-  if (ptpconfig->TimestampUpdateMode == ENABLE)
-  {
-    SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSFCU);
-  }
-
-  /* Set PTP Configuration done */
-  heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
-
-  /* Set Seconds */
-  time.Seconds = heth->Instance->PTPTSHR;
-  /* Set NanoSeconds */
-  time.NanoSeconds = heth->Instance->PTPTSLR;
-
-  HAL_ETH_PTP_SetTime(heth, &time);
-
-  /* Ptp Init */
-  SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTI);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the Ethernet PTP configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
-  *         the configuration information for PTP
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
-{
-  if (ptpconfig == NULL)
-  {
-    return HAL_ERROR;
-  }
-  ptpconfig->Timestamp = READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE);
-  ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->PTPTSCR,
-                                          ETH_PTPTSCR_TSFCU) >> ETH_PTPTSCR_TSFCU_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->PTPTSCR,
-                                       ETH_PTPTSCR_TSSARFE) >> ETH_PTPTSCR_TSSARFE_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->PTPTSCR,
-                                                ETH_PTPTSCR_TSSSR) >> ETH_PTPTSCR_TSSSR_Pos) > 0U)
-                                     ? ENABLE : DISABLE;
-  ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->PTPTSCR,
-                                      ETH_PTPTSCR_TSPTPPSV2E) >> ETH_PTPTSCR_TSPTPPSV2E_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->PTPTSCR,
-                                            ETH_PTPTSCR_TSSPTPOEFE) >> ETH_PTPTSCR_TSSPTPOEFE_Pos) > 0U)
-                                 ? ENABLE : DISABLE;
-  ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->PTPTSCR,
-                                        ETH_PTPTSCR_TSSIPV6FE) >> ETH_PTPTSCR_TSSIPV6FE_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->PTPTSCR,
-                                        ETH_PTPTSCR_TSSIPV4FE) >> ETH_PTPTSCR_TSSIPV4FE_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->PTPTSCR,
-                                         ETH_PTPTSCR_TSSEME) >> ETH_PTPTSCR_TSSEME_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->PTPTSCR,
-                                          ETH_PTPTSCR_TSSMRME) >> ETH_PTPTSCR_TSSMRME_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->PTPTSCR,
-                                          ETH_PTPTSCR_TSPFFMAE) >> ETH_PTPTSCR_TSPFFMAE_Pos) > 0U) ? ENABLE : DISABLE;
-  ptpconfig->TimestampClockType = ((READ_BIT(heth->Instance->PTPTSCR,
-                                             ETH_PTPTSCR_TSCNT) >> ETH_PTPTSCR_TSCNT_Pos) > 0U) ? ENABLE : DISABLE;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set Seconds and Nanoseconds for the Ethernet PTP registers.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
-  *         time to set
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
-{
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* Set Seconds */
-    heth->Instance->PTPTSHUR = time->Seconds;
-
-    /* Set NanoSeconds */
-    heth->Instance->PTPTSLUR = time->NanoSeconds;
-
-    /* the system time is updated */
-    SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Get Seconds and Nanoseconds for the Ethernet PTP registers.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
-  *         time to get
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
-{
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* Get Seconds */
-    time->Seconds = heth->Instance->PTPTSHR;
-    /* Get NanoSeconds */
-    time->NanoSeconds = heth->Instance->PTPTSLR;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Update time for the Ethernet PTP registers.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
-  *         the time update information
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
-                                            ETH_TimeTypeDef *timeoffset)
-{
-  int32_t addendtime ;
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    if (ptpoffsettype ==  HAL_ETH_PTP_NEGATIVE_UPDATE)
-    {
-      /* Set Seconds update */
-      heth->Instance->PTPTSHUR = ETH_PTPTSHR_VALUE - timeoffset->Seconds + 1U;
-
-      if (READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSSR) == ETH_PTPTSCR_TSSSR)
-      {
-        /* Set nanoSeconds update */
-        heth->Instance->PTPTSLUR = ETH_PTPTSLR_VALUE - timeoffset->NanoSeconds;
-      }
-      else
-      {
-        heth->Instance->PTPTSLUR = ETH_PTPTSHR_VALUE - timeoffset->NanoSeconds + 1U;
-      }
-
-      /* adjust negative addend register */
-      addendtime = - timeoffset->NanoSeconds;
-      HAL_ETH_PTP_AddendUpdate(heth, addendtime);
-
-    }
-    else
-    {
-      /* Set Seconds update */
-      heth->Instance->PTPTSHUR = timeoffset->Seconds;
-      /* Set nanoSeconds update */
-      heth->Instance->PTPTSLUR = timeoffset->NanoSeconds;
-
-      /* adjust positive addend register */
-      addendtime = timeoffset->NanoSeconds;
-      HAL_ETH_PTP_AddendUpdate(heth, addendtime);
-
-    }
-
-    SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Update the Addend register
-  * @param  heth: Pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  timeoffset: The value of the time offset to be added to
-  *         the addend register in Nanoseconds
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset)
-{
-  uint32_t tmpreg;
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* update the addend register */
-
-    tmpreg = READ_REG(heth->Instance->PTPTSAR);
-    tmpreg += timeoffset ;
-    WRITE_REG(heth->Instance->PTPTSAR, tmpreg);
-
-    SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU);
-    while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0)
-    {
-
-    }
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-/**
-  * @brief  Insert Timestamp in transmission.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
-{
-  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
-  uint32_t descidx = dmatxdesclist->CurTxDesc;
-  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* Enable Time Stamp transmission */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TTSE);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Get transmission timestamp.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
-  *         transmission timestamp
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
-{
-  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
-  uint32_t idx =       dmatxdesclist->releaseIndex;
-  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
-
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* Get timestamp low */
-    timestamp->TimeStampLow = dmatxdesc->DESC0;
-    /* Get timestamp high */
-    timestamp->TimeStampHigh = dmatxdesc->DESC1;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Get receive timestamp.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
-  *         receive timestamp
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
-{
-  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
-  {
-    /* Get timestamp low */
-    timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
-    /* Get timestamp high */
-    timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Register the Tx Ptp callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  txPtpCallback: Function to handle Ptp transmission
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback)
-{
-  if (txPtpCallback == NULL)
-  {
-    /* No buffer to save */
-    return HAL_ERROR;
-  }
-  /* Set Function to handle Tx Ptp */
-  heth->txPtpCallback = txPtpCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unregister the Tx Ptp callback.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
-{
-  /* Set function to allocate buffer */
-  heth->txPtpCallback = HAL_ETH_TxPtpCallback;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Tx Ptp callback.
-  * @param  buff: pointer to application buffer
-  * @param  timestamp: pointer to ETH_TimeStampTypeDef structure that contains
-  *         transmission timestamp
-  * @retval None
-  */
-__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(buff);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_TxPtpCallback could be implemented in the user file
-  */
-}
-#endif  /* HAL_ETH_USE_PTP */
-
-/**
-  * @brief  This function handles ETH interrupt request.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
-{
-  uint32_t mac_flag = READ_REG(heth->Instance->MACSR);
-  uint32_t dma_flag = READ_REG(heth->Instance->DMASR);
-  uint32_t dma_itsource = READ_REG(heth->Instance->DMAIER);
-  uint32_t exti_flag = READ_REG(EXTI->PR);
-
-  /* Packet received */
-  if (((dma_flag & ETH_DMASR_RS) != 0U) && ((dma_itsource & ETH_DMAIER_RIE) != 0U))
-  {
-    /* Clear the Eth DMA Rx IT pending bits */
-    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS);
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /*Call registered Receive complete callback*/
-    heth->RxCpltCallback(heth);
-#else
-    /* Receive complete callback */
-    HAL_ETH_RxCpltCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  }
-
-  /* Packet transmitted */
-  if (((dma_flag & ETH_DMASR_TS) != 0U) && ((dma_itsource & ETH_DMAIER_TIE) != 0U))
-  {
-    /* Clear the Eth DMA Tx IT pending bits */
-    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS);
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /*Call registered Transmit complete callback*/
-    heth->TxCpltCallback(heth);
-#else
-    /* Transfer complete callback */
-    HAL_ETH_TxCpltCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  }
-
-  /* ETH DMA Error */
-  if (((dma_flag & ETH_DMASR_AIS) != 0U) && ((dma_itsource & ETH_DMAIER_AISE) != 0U))
-  {
-    heth->ErrorCode |= HAL_ETH_ERROR_DMA;
-    /* if fatal bus error occurred */
-    if ((dma_flag & ETH_DMASR_FBES) != 0U)
-    {
-      /* Get DMA error code  */
-      heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS));
-
-      /* Disable all interrupts */
-      __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE);
-
-      /* Set HAL state to ERROR */
-      heth->gState = HAL_ETH_STATE_ERROR;
-    }
-    else
-    {
-      /* Get DMA error status  */
-      heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
-                                                            ETH_DMASR_RBUS | ETH_DMASR_AIS));
-
-      /* Clear the interrupt summary flag */
-      __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS |
-                                    ETH_DMASR_RBUS | ETH_DMASR_AIS));
-    }
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered Error callback*/
-    heth->ErrorCallback(heth);
-#else
-    /* Ethernet DMA Error callback */
-    HAL_ETH_ErrorCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  }
-
-
-  /* ETH PMT IT */
-  if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
-  {
-    /* Get MAC Wake-up source and clear the status register pending bit */
-    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR));
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered PMT callback*/
-    heth->PMTCallback(heth);
-#else
-    /* Ethernet PMT callback */
-    HAL_ETH_PMTCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-    heth->MACWakeUpEvent = (uint32_t)(0x0U);
-  }
-
-
-  /* check ETH WAKEUP exti flag */
-  if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
-  {
-    /* Clear ETH WAKEUP Exti pending bit */
-    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered WakeUp callback*/
-    heth->WakeUpCallback(heth);
-#else
-    /* ETH WAKEUP callback */
-    HAL_ETH_WakeUpCallback(heth);
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_TxCpltCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_RxCpltCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Ethernet transfer error callbacks
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_ErrorCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Ethernet Power Management module IT callback
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_PMTCallback could be implemented in the user file
-  */
-}
-
-
-/**
-  * @brief  ETH WAKEUP interrupt callback
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ETH_WakeUpCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Read a PHY register
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
-  * @param  PHYReg: PHY register address, must be a value from 0 to 31
-  * @param pRegValue: parameter to hold read value
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                          uint32_t *pRegValue)
-{
-  uint32_t tmpreg1;
-  uint32_t tickstart;
-
-  /* Get the ETHERNET MACMIIAR value */
-  tmpreg1 = heth->Instance->MACMIIAR;
-
-  /* Keep only the CSR Clock Range CR[2:0] bits value */
-  tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-
-  /* Prepare the MII address register value */
-  tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA);                        /* Set the PHY device address   */
-  tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR);                /* Set the PHY register address */
-  tmpreg1 &= ~ETH_MACMIIAR_MW;                                            /* Set the read mode            */
-  tmpreg1 |= ETH_MACMIIAR_MB;                                             /* Set the MII Busy bit         */
-
-  /* Write the result value into the MII Address register */
-  heth->Instance->MACMIIAR = tmpreg1;
-
-
-  tickstart = HAL_GetTick();
-
-  /* Check for the Busy flag */
-  while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
-  {
-    /* Check for the Timeout */
-    if ((HAL_GetTick() - tickstart) > PHY_READ_TO)
-    {
-      return HAL_ERROR;
-    }
-
-    tmpreg1 = heth->Instance->MACMIIAR;
-  }
-
-  /* Get MACMIIDR value */
-  *pRegValue = (uint16_t)(heth->Instance->MACMIIDR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Writes to a PHY register.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
-  * @param  PHYReg: PHY register address, must be a value from 0 to 31
-  * @param  RegValue: the value to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
-                                           uint32_t RegValue)
-{
-  uint32_t tmpreg1;
-  uint32_t tickstart;
-
-  /* Get the ETHERNET MACMIIAR value */
-  tmpreg1 = heth->Instance->MACMIIAR;
-
-  /* Keep only the CSR Clock Range CR[2:0] bits value */
-  tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
-
-  /* Prepare the MII register address value */
-  tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA);                      /* Set the PHY device address */
-  tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR);              /* Set the PHY register address */
-  tmpreg1 |= ETH_MACMIIAR_MW;                                           /* Set the write mode */
-  tmpreg1 |= ETH_MACMIIAR_MB;                                           /* Set the MII Busy bit */
-
-  /* Give the value to the MII data register */
-  heth->Instance->MACMIIDR = (uint16_t)RegValue;
-
-  /* Write the result value into the MII Address register */
-  heth->Instance->MACMIIAR = tmpreg1;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check for the Busy flag */
-  while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
-  {
-    /* Check for the Timeout */
-    if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO)
-    {
-      return HAL_ERROR;
-    }
-
-    tmpreg1 = heth->Instance->MACMIIAR;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   ETH control functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the ETH
-    peripheral.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Get the configuration of the MAC and MTL subsystems.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
-  *         the configuration of the MAC.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
-{
-  if (macconf == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Get MAC parameters */
-  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
-  macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
-  macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_RD) >> 9) == 0U) ? ENABLE : DISABLE;
-  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U)
-                                        ? ENABLE : DISABLE;
-  macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ROD) >> 13) == 0U) ? ENABLE : DISABLE;
-  macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
-  macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
-  macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
-  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 22) == 0U) ? ENABLE : DISABLE;
-  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE;
-  macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE;
-  macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG);
-  macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE;
-  macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSTF) >> 25U) > 0U) ? ENABLE : DISABLE;
-
-  macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE;
-  macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE;
-  macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT);
-  macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16);
-  macconf->ReceiveFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) >> 2U) > 0U) ? ENABLE : DISABLE;
-  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U)
-                                      ? ENABLE : DISABLE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the configuration of the DMA.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
-  *         the configuration of the ETH DMA.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
-{
-  if (dmaconf == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR,
-                                     (ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1));
-  dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 25U) > 0U) ? ENABLE : DISABLE;
-  dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB);
-  dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP);
-  dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_PBL);
-  dmaconf->EnhancedDescriptorFormat = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_EDE) >> 7) > 0U) ? ENABLE : DISABLE;
-  dmaconf->DescriptorSkipLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2;
-
-  dmaconf->DropTCPIPChecksumErrorFrame = ((READ_BIT(heth->Instance->DMAOMR,
-                                                    ETH_DMAOMR_DTCEFD) >> 26) > 0U) ? DISABLE : ENABLE;
-  dmaconf->ReceiveStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RSF) >> 25) > 0U) ? ENABLE : DISABLE;
-  dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FTF) >> 20) > 0U) ? DISABLE : ENABLE;
-  dmaconf->TransmitStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TSF) >> 21) > 0U) ? ENABLE : DISABLE;
-  dmaconf->TransmitThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TTC);
-  dmaconf->ForwardErrorFrames = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FEF) >> 7) > 0U) ? ENABLE : DISABLE;
-  dmaconf->ForwardUndersizedGoodFrames = ((READ_BIT(heth->Instance->DMAOMR,
-                                                    ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE;
-  dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC);
-  dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the MAC configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
-  *         the configuration of the MAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
-{
-  if (macconf == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    ETH_SetMACConfig(heth, macconf);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Set the ETH DMA configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
-  *         the configuration of the ETH DMA.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
-{
-  if (dmaconf == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  if (heth->gState == HAL_ETH_STATE_READY)
-  {
-    ETH_SetDMAConfig(heth, dmaconf);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configures the Clock range of ETH MDIO interface.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
-{
-  uint32_t hclk;
-  uint32_t tmpreg;
-
-  /* Get the ETHERNET MACMIIAR value */
-  tmpreg = (heth->Instance)->MACMIIAR;
-  /* Clear CSR Clock Range CR[2:0] bits */
-  tmpreg &= ETH_MACMIIAR_CR_MASK;
-
-  /* Get hclk frequency value */
-  hclk = HAL_RCC_GetHCLKFreq();
-
-  /* Set CR bits depending on hclk value */
-  if (hclk < 35000000U)
-  {
-    /* CSR Clock Range between 0-35 MHz */
-    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
-  }
-  else if (hclk < 60000000U)
-  {
-    /* CSR Clock Range between 35-60 MHz */
-    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
-  }
-  else if (hclk < 100000000U)
-  {
-    /* CSR Clock Range between 60-100 MHz */
-    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
-  }
-  else if (hclk < 150000000U)
-  {
-    /* CSR Clock Range between 100-150 MHz */
-    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
-  }
-  else /* (hclk >= 150000000)  */
-  {
-    /* CSR Clock >= 150 MHz */
-    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
-  }
-
-  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
-  (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
-}
-
-/**
-  * @brief  Set the ETH MAC (L2) Filters configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
-  *         the configuration of the ETH MAC filters.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
-{
-  uint32_t filterconfig;
-  uint32_t tmpreg1;
-
-  if (pFilterConfig == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
-                  ((uint32_t)pFilterConfig->HashUnicast << 1) |
-                  ((uint32_t)pFilterConfig->HashMulticast << 2)  |
-                  ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
-                  ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
-                  ((uint32_t)((pFilterConfig->BroadcastFilter == ENABLE) ? 1U : 0U) << 5) |
-                  ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
-                  ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
-                  ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
-                  ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
-                  pFilterConfig->ControlPacketsFilter);
-
-  MODIFY_REG(heth->Instance->MACFFR, ETH_MACFFR_MASK, filterconfig);
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACFFR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACFFR = tmpreg1;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the ETH MAC (L2) Filters configuration.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
-  *         the configuration of the ETH MAC filters.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
-{
-  if (pFilterConfig == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PM)) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HU) >> 1) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HM) >> 2) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR,
-                                                       ETH_MACFFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PAM) >> 4) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PCF);
-  pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR,
-                                                      ETH_MACFFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HPF) >> 10) > 0U)
-                                       ? ENABLE : DISABLE;
-  pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the source MAC Address to be matched.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  AddrNbr: The MAC address to configure
-  *          This parameter must be a value of the following:
-  *            ETH_MAC_ADDRESS1
-  *            ETH_MAC_ADDRESS2
-  *            ETH_MAC_ADDRESS3
-  * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
-                                                const uint8_t *pMACAddr)
-{
-  uint32_t macaddrlr;
-  uint32_t macaddrhr;
-
-  if (pMACAddr == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Get mac addr high reg offset */
-  macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr);
-  /* Get mac addr low reg offset */
-  macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr);
-
-  /* Set MAC addr bits 32 to 47 */
-  (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
-  /* Set MAC addr bits 0 to 31 */
-  (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
-                                   ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
-
-  /* Enable address and set source address bit */
-  (*(__IO uint32_t *)macaddrhr) |= (ETH_MACA1HR_AE | ETH_MACA1HR_SA);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the ETH Hash Table Value.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pHashTable: pointer to a table of two 32 bit values, that contains
-  *         the 64 bits of the hash table.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
-{
-  uint32_t tmpreg1;
-  if (pHashTable == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  heth->Instance->MACHTHR = pHashTable[0];
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACHTHR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACHTHR = tmpreg1;
-
-  heth->Instance->MACHTLR = pHashTable[1];
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACHTLR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACHTLR = tmpreg1;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the VLAN Identifier for Rx packets
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  ComparisonBits: 12 or 16 bit comparison mode
-            must be a value of @ref ETH_VLAN_Tag_Comparison
-  * @param  VLANIdentifier: VLAN Identifier value
-  * @retval None
-  */
-void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
-{
-  uint32_t tmpreg1;
-  MODIFY_REG(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTI, VLANIdentifier);
-  if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
-  {
-    CLEAR_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC);
-  }
-  else
-  {
-    SET_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC);
-  }
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACVLANTR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACVLANTR = tmpreg1;
-}
-
-/**
-  * @brief  Enters the Power down mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
-  *         that contains the Power Down configuration
-  * @retval None.
-  */
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
-{
-  uint32_t powerdownconfig;
-
-  powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << ETH_MACPMTCSR_MPE_Pos) |
-                     ((uint32_t)pPowerDownConfig->WakeUpPacket << ETH_MACPMTCSR_WFE_Pos) |
-                     ((uint32_t)pPowerDownConfig->GlobalUnicast << ETH_MACPMTCSR_GU_Pos) |
-                     ETH_MACPMTCSR_PD);
-
-  MODIFY_REG(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_MASK, powerdownconfig);
-}
-
-/**
-  * @brief  Exits from the Power down mode.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None.
-  */
-void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
-{
-  uint32_t tmpreg1;
-
-  /* clear wake up sources */
-  CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFE | ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU);
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACPMTCSR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACPMTCSR = tmpreg1;
-
-  if (READ_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD) != 0U)
-  {
-    /* Exit power down mode */
-    CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD);
-
-    /* Wait until the write operation will be taken into account :
-    at least four TX_CLK/RX_CLK clock cycles */
-    tmpreg1 = (heth->Instance)->MACPMTCSR;
-    HAL_Delay(ETH_REG_WRITE_DELAY);
-    (heth->Instance)->MACPMTCSR = tmpreg1;
-  }
-
-  /* Disable PMT interrupt */
-  SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_PMTIM);
-}
-
-/**
-  * @brief  Set the WakeUp filter.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pFilter: pointer to filter registers values
-  * @param  Count: number of filter registers, must be from 1 to 8.
-  * @retval None.
-  */
-HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
-{
-  uint32_t regindex;
-
-  if (pFilter == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Reset Filter Pointer */
-  SET_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFFRPR);
-
-  /* Wake up packet filter config */
-  for (regindex = 0; regindex < Count; regindex++)
-  {
-    /* Write filter regs */
-    WRITE_REG(heth->Instance->MACRWUFFR, pFilter[regindex]);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   ETH State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   ETH communication process, return Peripheral Errors occurred during communication
-   process
-
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the ETH state.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL state
-  */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
-{
-  return heth->gState;
-}
-
-/**
-  * @brief  Returns the ETH error code
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval ETH Error Code
-  */
-uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
-{
-  return heth->ErrorCode;
-}
-
-/**
-  * @brief  Returns the ETH DMA error code
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval ETH DMA Error Code
-  */
-uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
-{
-  return heth->DMAErrorCode;
-}
-
-/**
-  * @brief  Returns the ETH MAC error code
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval ETH MAC Error Code
-  */
-uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
-{
-  return heth->MACErrorCode;
-}
-
-/**
-  * @brief  Returns the ETH MAC WakeUp event source
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval ETH MAC WakeUp event source
-  */
-uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
-{
-  return heth->MACWakeUpEvent;
-}
-
-/**
-  * @brief  Returns the ETH Tx Buffers in use number
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval ETH Tx Buffers in use number
-  */
-uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth)
-{
-  return heth->TxDescList.BuffersInUse;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup ETH_Private_Functions   ETH Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Clears the ETHERNET transmit FIFO.
-  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Set the Flush Transmit FIFO bit */
-  (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
-
-  /* Wait until the write operation will be taken into account:
-     at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg = (heth->Instance)->DMAOMR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->DMAOMR = tmpreg;
-}
-
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
-{
-  uint32_t tmpreg1;
-
-  /*------------------------ ETHERNET MACCR Configuration --------------------*/
-  /* Get the ETHERNET MACCR value */
-  tmpreg1 = (heth->Instance)->MACCR;
-  /* Clear CSTF, WD, PCE, PS, TE and RE bits */
-  tmpreg1 &= ETH_MACCR_CLEAR_MASK;
-
-  tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) |
-                        ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) |
-                        ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) |
-                        (uint32_t)macconf->InterPacketGapVal |
-                        ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) |
-                        macconf->Speed |
-                        ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) |
-                        ((uint32_t)macconf->LoopbackMode << 12U) |
-                        macconf->DuplexMode |
-                        ((uint32_t)macconf->ChecksumOffload << 10U) |
-                        ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) |
-                        ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) |
-                        macconf->BackOffLimit |
-                        ((uint32_t)macconf->DeferralCheck << 4U));
-
-  /* Write to ETHERNET MACCR */
-  (heth->Instance)->MACCR = (uint32_t)tmpreg1;
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACCR = tmpreg1;
-
-  /*----------------------- ETHERNET MACFCR Configuration --------------------*/
-
-  /* Get the ETHERNET MACFCR value */
-  tmpreg1 = (heth->Instance)->MACFCR;
-  /* Clear xx bits */
-  tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
-
-  tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
-                        ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) |
-                        macconf->PauseLowThreshold |
-                        ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) |
-                        ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) |
-                        ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U));
-
-  /* Write to ETHERNET MACFCR */
-  (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
-
-  /* Wait until the write operation will be taken into account :
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->MACFCR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->MACFCR = tmpreg1;
-}
-
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
-{
-  uint32_t tmpreg1;
-
-  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
-  /* Get the ETHERNET DMAOMR value */
-  tmpreg1 = (heth->Instance)->DMAOMR;
-  /* Clear xx bits */
-  tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
-
-  tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) |
-                        ((uint32_t)dmaconf->ReceiveStoreForward << 25U) |
-                        ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) |
-                        ((uint32_t)dmaconf->TransmitStoreForward << 21U) |
-                        dmaconf->TransmitThresholdControl |
-                        ((uint32_t)dmaconf->ForwardErrorFrames << 7U) |
-                        ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) |
-                        dmaconf->ReceiveThresholdControl |
-                        ((uint32_t)dmaconf->SecondFrameOperate << 2U));
-
-  /* Write to ETHERNET DMAOMR */
-  (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
-
-  /* Wait until the write operation will be taken into account:
-  at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->DMAOMR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->DMAOMR = tmpreg1;
-
-  /*----------------------- ETHERNET DMABMR Configuration --------------------*/
-  (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) |
-                                        dmaconf->BurstMode |
-                                        dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or
-                                                                       Rx it is applied for the other */
-                                        dmaconf->TxDMABurstLength |
-                                        ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) |
-                                        (dmaconf->DescriptorSkipLength << 2U) |
-                                        dmaconf->DMAArbitration |
-                                        ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
-
-  /* Wait until the write operation will be taken into account:
-     at least four TX_CLK/RX_CLK clock cycles */
-  tmpreg1 = (heth->Instance)->DMABMR;
-  HAL_Delay(ETH_REG_WRITE_DELAY);
-  (heth->Instance)->DMABMR = tmpreg1;
-}
-
-/**
-  * @brief  Configures Ethernet MAC and DMA with default parameters.
-  *         called by HAL_ETH_Init() API.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval HAL status
-  */
-static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
-{
-  ETH_MACConfigTypeDef macDefaultConf;
-  ETH_DMAConfigTypeDef dmaDefaultConf;
-
-  /*--------------- ETHERNET MAC registers default Configuration --------------*/
-  macDefaultConf.Watchdog = ENABLE;
-  macDefaultConf.Jabber = ENABLE;
-  macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT;
-  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
-  macDefaultConf.ReceiveOwn = ENABLE;
-  macDefaultConf.LoopbackMode = DISABLE;
-  macDefaultConf.CRCStripTypePacket = ENABLE;
-  macDefaultConf.ChecksumOffload = ENABLE;
-  macDefaultConf.RetryTransmission = DISABLE;
-  macDefaultConf.AutomaticPadCRCStrip = DISABLE;
-  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
-  macDefaultConf.DeferralCheck = DISABLE;
-  macDefaultConf.PauseTime = 0x0U;
-  macDefaultConf.ZeroQuantaPause = DISABLE;
-  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
-  macDefaultConf.ReceiveFlowControl = DISABLE;
-  macDefaultConf.TransmitFlowControl = DISABLE;
-  macDefaultConf.Speed = ETH_SPEED_100M;
-  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
-  macDefaultConf.UnicastPausePacketDetect = DISABLE;
-
-  /* MAC default configuration */
-  ETH_SetMACConfig(heth, &macDefaultConf);
-
-  /*--------------- ETHERNET DMA registers default Configuration --------------*/
-  dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE;
-  dmaDefaultConf.ReceiveStoreForward = ENABLE;
-  dmaDefaultConf.FlushRxPacket = ENABLE;
-  dmaDefaultConf.TransmitStoreForward = ENABLE;
-  dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
-  dmaDefaultConf.ForwardErrorFrames = DISABLE;
-  dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE;
-  dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
-  dmaDefaultConf.SecondFrameOperate = ENABLE;
-  dmaDefaultConf.AddressAlignedBeats = ENABLE;
-  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
-  dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
-  dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
-  dmaDefaultConf.EnhancedDescriptorFormat = ENABLE;
-  dmaDefaultConf.DescriptorSkipLength = 0x0U;
-  dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
-
-  /* DMA default configuration */
-  ETH_SetDMAConfig(heth, &dmaDefaultConf);
-}
-/**
-  * @brief  Configures the selected MAC address.
-  * @param  heth pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  MacAddr The MAC address to configure
-  *          This parameter can be one of the following values:
-  *             @arg ETH_MAC_Address0: MAC Address0
-  *             @arg ETH_MAC_Address1: MAC Address1
-  *             @arg ETH_MAC_Address2: MAC Address2
-  *             @arg ETH_MAC_Address3: MAC Address3
-  * @param  Addr Pointer to MAC address buffer data (6 bytes)
-  * @retval HAL status
-  */
-static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
-{
-  uint32_t tmpreg1;
-
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-
-  /* Calculate the selected MAC address high register */
-  tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
-  /* Load the selected MAC address high register */
-  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
-  /* Calculate the selected MAC address low register */
-  tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
-
-  /* Load the selected MAC address low register */
-  (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
-}
-
-/**
-  * @brief  Initializes the DMA Tx descriptors.
-  *         called by HAL_ETH_Init() API.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
-{
-  ETH_DMADescTypeDef *dmatxdesc;
-  uint32_t i;
-
-  /* Fill each DMATxDesc descriptor with the right values */
-  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
-  {
-    dmatxdesc = heth->Init.TxDesc + i;
-
-    WRITE_REG(dmatxdesc->DESC0, 0x0U);
-    WRITE_REG(dmatxdesc->DESC1, 0x0U);
-    WRITE_REG(dmatxdesc->DESC2, 0x0U);
-    WRITE_REG(dmatxdesc->DESC3, 0x0U);
-
-    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
-
-    /* Set Second Address Chained bit */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH);
-
-    if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U))
-    {
-      WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U));
-    }
-    else
-    {
-      WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc));
-    }
-
-    /* Set the DMA Tx descriptors checksum insertion */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL);
-  }
-
-  heth->TxDescList.CurTxDesc = 0;
-
-  /* Set Transmit Descriptor List Address */
-  WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc);
-}
-
-/**
-  * @brief  Initializes the DMA Rx descriptors in chain mode.
-  *         called by HAL_ETH_Init() API.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
-{
-  ETH_DMADescTypeDef *dmarxdesc;
-  uint32_t i;
-
-  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
-  {
-    dmarxdesc =  heth->Init.RxDesc + i;
-
-    WRITE_REG(dmarxdesc->DESC0, 0x0U);
-    WRITE_REG(dmarxdesc->DESC1, 0x0U);
-    WRITE_REG(dmarxdesc->DESC2, 0x0U);
-    WRITE_REG(dmarxdesc->DESC3, 0x0U);
-    WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
-    WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
-
-    /* Set Own bit of the Rx descriptor Status */
-    dmarxdesc->DESC0 = ETH_DMARXDESC_OWN;
-
-    /* Set Buffer1 size and Second Address Chained bit */
-    dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH;
-
-    /* Enable Ethernet DMA Rx Descriptor interrupt */
-    dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC;
-    /* Set Rx descritors addresses */
-    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
-
-    if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U))
-    {
-      WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U));
-    }
-    else
-    {
-      WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc));
-    }
-  }
-
-  WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
-  WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
-  WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
-  WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
-  WRITE_REG(heth->RxDescList.ItMode, 0U);
-
-  /* Set Receive Descriptor List Address */
-  WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc);
-}
-
-/**
-  * @brief  Prepare Tx DMA descriptor before transmission.
-  *         called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  pTxConfig: Tx packet configuration
-  * @param  ItMode: Enable or disable Tx EOT interrupt
-  * @retval Status
-  */
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
-                                           uint32_t ItMode)
-{
-  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
-  uint32_t descidx = dmatxdesclist->CurTxDesc;
-  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
-  uint32_t idx;
-  uint32_t descnbr = 0;
-  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
-  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
-  uint32_t           bd_count = 0;
-  uint32_t primask_bit;
-
-  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-  if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN)
-      || (dmatxdesclist->PacketAddress[descidx] != NULL))
-  {
-    return HAL_ETH_ERROR_BUSY;
-  }
-
-
-  descnbr += 1U;
-
-  /* Set header or buffer 1 address */
-  WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer);
-
-  /* Set header or buffer 1 Length */
-  MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len);
-
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
-  {
-    MODIFY_REG(dmatxdesc->DESC0, ETH_DMATXDESC_CIC, pTxConfig->ChecksumCtrl);
-  }
-
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
-  {
-    MODIFY_REG(dmatxdesc->DESC0, ETH_CRC_PAD_DISABLE, pTxConfig->CRCPadCtrl);
-  }
-
-
-  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
-  {
-    /* Set Vlan Type */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_VF);
-  }
-
-  /* Mark it as First Descriptor */
-  SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS);
-
-  /* only if the packet is split into more than one descriptors > 1 */
-  while (txbuffer->next != NULL)
-  {
-    /* Clear the LD bit of previous descriptor */
-    CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS);
-    if (ItMode != ((uint32_t)RESET))
-    {
-      /* Set Interrupt on completion bit */
-      SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC);
-    }
-    else
-    {
-      /* Clear Interrupt on completion bit */
-      CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC);
-    }
-    /* Increment current tx descriptor index */
-    INCR_TX_DESC_INDEX(descidx, 1U);
-    /* Get current descriptor address */
-    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
-    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-    if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN)
-        || (dmatxdesclist->PacketAddress[descidx] != NULL))
-    {
-      descidx = firstdescidx;
-      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-
-      /* clear previous desc own bit */
-      for (idx = 0; idx < descnbr; idx ++)
-      {
-        /* Ensure rest of descriptor is written to RAM before the OWN bit */
-        __DMB();
-
-        CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN);
-
-        /* Increment current tx descriptor index */
-        INCR_TX_DESC_INDEX(descidx, 1U);
-        /* Get current descriptor address */
-        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
-      }
-
-      return HAL_ETH_ERROR_BUSY;
-    }
-
-    /* Clear the FD bit of new Descriptor */
-    CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS);
-
-    descnbr += 1U;
-
-    /* Get the next Tx buffer in the list */
-    txbuffer = txbuffer->next;
-
-    /* Set header or buffer 1 address */
-    WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer);
-
-    /* Set header or buffer 1 Length */
-    MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len);
-
-    bd_count += 1U;
-
-    /* Ensure rest of descriptor is written to RAM before the OWN bit */
-    __DMB();
-    /* Set Own bit */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN);
-  }
-
-  if (ItMode != ((uint32_t)RESET))
-  {
-    /* Set Interrupt on completion bit */
-    SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC);
-  }
-  else
-  {
-    /* Clear Interrupt on completion bit */
-    CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC);
-  }
-
-  /* Mark it as LAST descriptor */
-  SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS);
-
-  /* Get address of first descriptor */
-  dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
-  /* Ensure rest of descriptor is written to RAM before the OWN bit */
-  __DMB();
-  /* set OWN bit of FIRST descriptor */
-  SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN);
-  /* Save the current packet address to expose it to the application */
-  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
-
-  dmatxdesclist->CurTxDesc = descidx;
-
-  /* Enter critical section */
-  primask_bit = __get_PRIMASK();
-  __set_PRIMASK(1);
-
-  dmatxdesclist->BuffersInUse += bd_count + 1U;
-
-  /* Exit critical section: restore previous priority mask */
-  __set_PRIMASK(primask_bit);
-
-  /* Return function status */
-  return HAL_ETH_ERROR_NONE;
-}
-
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
-{
-  /* Init the ETH Callback settings */
-  heth->TxCpltCallback   = HAL_ETH_TxCpltCallback;    /* Legacy weak TxCpltCallback   */
-  heth->RxCpltCallback   = HAL_ETH_RxCpltCallback;    /* Legacy weak RxCpltCallback   */
-  heth->ErrorCallback    = HAL_ETH_ErrorCallback;     /* Legacy weak ErrorCallback */
-  heth->PMTCallback      = HAL_ETH_PMTCallback;       /* Legacy weak PMTCallback      */
-  heth->WakeUpCallback   = HAL_ETH_WakeUpCallback;    /* Legacy weak WakeUpCallback   */
-  heth->rxLinkCallback   = HAL_ETH_RxLinkCallback;    /* Legacy weak RxLinkCallback   */
-  heth->txFreeCallback   = HAL_ETH_TxFreeCallback;    /* Legacy weak TxFreeCallback   */
-#ifdef HAL_ETH_USE_PTP
-  heth->txPtpCallback    = HAL_ETH_TxPtpCallback;     /* Legacy weak TxPtpCallback   */
-#endif /* HAL_ETH_USE_PTP */
-  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */
-}
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ETH */
-
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
diff --git a/Volume-Controller-STM.ioc b/Volume-Controller-STM.ioc
index 40a3096..3e157e4 100644
--- a/Volume-Controller-STM.ioc
+++ b/Volume-Controller-STM.ioc
@@ -2,56 +2,54 @@
 CAD.formats=
 CAD.pinconfig=
 CAD.provider=
-ETH.IPParameters=MediaInterface,PHY_Name,PHY_Value,PhyAddress
-ETH.MediaInterface=HAL_ETH_RMII_MODE
-ETH.PHY_Name=LAN8742A_PHY_ADDRESS
-ETH.PHY_Value=0
-ETH.PhyAddress=0
 File.Version=6
 KeepUserPlacement=false
 Mcu.CPN=STM32F767ZIT6
 Mcu.Family=STM32F7
 Mcu.IP0=CORTEX_M7
-Mcu.IP1=ETH
-Mcu.IP2=NVIC
-Mcu.IP3=RCC
-Mcu.IP4=SYS
-Mcu.IP5=USART3
-Mcu.IP6=USB_OTG_FS
-Mcu.IPNb=7
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=USART3
+Mcu.IP5=USB_OTG_FS
+Mcu.IPNb=6
 Mcu.Name=STM32F767ZITx
 Mcu.Package=LQFP144
 Mcu.Pin0=PC13
 Mcu.Pin1=PC14/OSC32_IN
-Mcu.Pin10=PC5
-Mcu.Pin11=PB0
-Mcu.Pin12=PB13
-Mcu.Pin13=PB14
-Mcu.Pin14=PD8
-Mcu.Pin15=PD9
-Mcu.Pin16=PG6
-Mcu.Pin17=PG7
-Mcu.Pin18=PA8
-Mcu.Pin19=PA9
+Mcu.Pin10=PC4
+Mcu.Pin11=PC5
+Mcu.Pin12=PB0
+Mcu.Pin13=PE10
+Mcu.Pin14=PE12
+Mcu.Pin15=PE14
+Mcu.Pin16=PB13
+Mcu.Pin17=PB14
+Mcu.Pin18=PD8
+Mcu.Pin19=PD9
 Mcu.Pin2=PC15/OSC32_OUT
-Mcu.Pin20=PA10
-Mcu.Pin21=PA11
-Mcu.Pin22=PA12
-Mcu.Pin23=PA13
-Mcu.Pin24=PA14
-Mcu.Pin25=PG11
-Mcu.Pin26=PG13
-Mcu.Pin27=PB3
-Mcu.Pin28=PB7
-Mcu.Pin29=VP_SYS_VS_Systick
-Mcu.Pin3=PH0/OSC_IN
-Mcu.Pin4=PH1/OSC_OUT
-Mcu.Pin5=PC1
-Mcu.Pin6=PA1
-Mcu.Pin7=PA2
-Mcu.Pin8=PA7
-Mcu.Pin9=PC4
-Mcu.PinsNb=30
+Mcu.Pin20=PG6
+Mcu.Pin21=PG7
+Mcu.Pin22=PA8
+Mcu.Pin23=PA9
+Mcu.Pin24=PA10
+Mcu.Pin25=PA11
+Mcu.Pin26=PA12
+Mcu.Pin27=PA13
+Mcu.Pin28=PA14
+Mcu.Pin29=PG11
+Mcu.Pin3=PF2
+Mcu.Pin30=PG13
+Mcu.Pin31=PB3
+Mcu.Pin32=PB7
+Mcu.Pin33=VP_SYS_VS_Systick
+Mcu.Pin4=PH0/OSC_IN
+Mcu.Pin5=PH1/OSC_OUT
+Mcu.Pin6=PC1
+Mcu.Pin7=PA1
+Mcu.Pin8=PA2
+Mcu.Pin9=PA7
+Mcu.PinsNb=34
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F767ZITx
@@ -71,7 +69,6 @@ NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
 PA1.GPIOParameters=GPIO_Label
 PA1.GPIO_Label=RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
 PA1.Locked=true
-PA1.Mode=RMII
 PA1.Signal=ETH_REF_CLK
 PA10.GPIOParameters=GPIO_Label
 PA10.GPIO_Label=USB_ID
@@ -100,13 +97,11 @@ PA14.Signal=SYS_JTCK-SWCLK
 PA2.GPIOParameters=GPIO_Label
 PA2.GPIO_Label=RMII_MDIO [LAN8742A-CZ-TR_MDIO]
 PA2.Locked=true
-PA2.Mode=RMII
 PA2.Signal=ETH_MDIO
 PA7.GPIOParameters=GPIO_Label
-PA7.GPIO_Label=RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+PA7.GPIO_Label=Pot UD
 PA7.Locked=true
-PA7.Mode=RMII
-PA7.Signal=ETH_CRS_DV
+PA7.Signal=GPIO_Output
 PA8.GPIOParameters=GPIO_Label
 PA8.GPIO_Label=USB_SOF [TP1]
 PA8.Locked=true
@@ -124,7 +119,6 @@ PB0.Signal=GPIO_Output
 PB13.GPIOParameters=GPIO_Label
 PB13.GPIO_Label=RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
 PB13.Locked=true
-PB13.Mode=RMII
 PB13.Signal=ETH_TXD1
 PB14.GPIOParameters=GPIO_Label
 PB14.GPIO_Label=LD3 [Red]
@@ -141,7 +135,6 @@ PB7.Signal=GPIO_Output
 PC1.GPIOParameters=GPIO_Label
 PC1.GPIO_Label=RMII_MDC [LAN8742A-CZ-TR_MDC]
 PC1.Locked=true
-PC1.Mode=RMII
 PC1.Signal=ETH_MDC
 PC13.GPIOParameters=GPIO_Label
 PC13.GPIO_Label=USER_Btn [B1]
@@ -156,12 +149,10 @@ PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
 PC4.GPIOParameters=GPIO_Label
 PC4.GPIO_Label=RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
 PC4.Locked=true
-PC4.Mode=RMII
 PC4.Signal=ETH_RXD0
 PC5.GPIOParameters=GPIO_Label
 PC5.GPIO_Label=RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
 PC5.Locked=true
-PC5.Mode=RMII
 PC5.Signal=ETH_RXD1
 PD8.GPIOParameters=GPIO_Label
 PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3]
@@ -173,15 +164,29 @@ PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2]
 PD9.Locked=true
 PD9.Mode=Asynchronous
 PD9.Signal=USART3_RX
+PE10.GPIOParameters=GPIO_Label
+PE10.GPIO_Label=Remote B
+PE10.Locked=true
+PE10.Signal=GPIO_Input
+PE12.GPIOParameters=GPIO_Label
+PE12.GPIO_Label=Remote C
+PE12.Locked=true
+PE12.Signal=GPIO_Input
+PE14.GPIOParameters=GPIO_Label
+PE14.GPIO_Label=Remote D
+PE14.Locked=true
+PE14.Signal=GPIO_Input
+PF2.GPIOParameters=GPIO_Label
+PF2.GPIO_Label=Pot CS
+PF2.Locked=true
+PF2.Signal=GPIO_Output
 PG11.GPIOParameters=GPIO_Label
 PG11.GPIO_Label=RMII_TX_EN [LAN8742A-CZ-TR_TXEN]
 PG11.Locked=true
-PG11.Mode=RMII
 PG11.Signal=ETH_TX_EN
 PG13.GPIOParameters=GPIO_Label
 PG13.GPIO_Label=RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
 PG13.Locked=true
-PG13.Mode=RMII
 PG13.Signal=ETH_TXD0
 PG6.GPIOParameters=GPIO_Label
 PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN]